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https://github.com/YosysHQ/yosys
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Rename csa_tree to arith_tree.
This commit is contained in:
nella
nella
parent
c3c577f333
commit
fc71719e6e
12 changed files with 90 additions and 90 deletions
197
tests/arith_tree/arith_tree_add_chains.ys
Normal file
197
tests/arith_tree/arith_tree_add_chains.ys
Normal file
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@ -0,0 +1,197 @@
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read_verilog <<EOT
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module add3(
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input [7:0] a, b, c,
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output [7:0] y
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);
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assign y = a + b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree
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select -assert-count 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add5(
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input [11:0] a, b, c, d, e,
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output [11:0] y
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);
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assign y = a + b + c + d + e;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add8(
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input [15:0] a, b, c, d, e, f, g, h,
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output [15:0] y
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);
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assign y = a + b + c + d + e + f + g + h;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree
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select -assert-count 6 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add16(
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input [15:0] a0, a1, a2, a3, a4, a5, a6, a7,
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input [15:0] a8, a9, a10, a11, a12, a13, a14, a15,
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output [15:0] y
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);
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assign y = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7
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+ a8 + a9 + a10 + a11 + a12 + a13 + a14 + a15;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree
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select -assert-count 14 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog -icells <<EOT
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module alu_add3(
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input [7:0] a, b, c,
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output [7:0] y
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);
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wire [7:0] tmp, x1, x2, co1, co2;
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// a + b
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$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
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alu1 (.A(a), .B(b), .BI(1'b0), .CI(1'b0), .Y(tmp), .X(x1), .CO(co1));
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// tmp + c
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$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
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alu2 (.A(tmp), .B(c), .BI(1'b0), .CI(1'b0), .Y(y), .X(x2), .CO(co2));
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endmodule
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EOT
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hierarchy -auto-top
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select -assert-count 2 t:$alu
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arith_tree
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opt_clean
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select -assert-count 1 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$alu
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design -reset
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read_verilog -icells <<EOT
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module alu_add4(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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wire [7:0] tmp1, tmp2, x1, x2, x3, co1, co2, co3;
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// a + b
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$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
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alu1 (.A(a), .B(b), .BI(1'b0), .CI(1'b0), .Y(tmp1), .X(x1), .CO(co1));
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// c + d
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$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
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alu2 (.A(c), .B(d), .BI(1'b0), .CI(1'b0), .Y(tmp2), .X(x2), .CO(co2));
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// tmp1 + tmp2
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$alu #(.A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(8), .A_SIGNED(0), .B_SIGNED(0))
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alu3 (.A(tmp1), .B(tmp2), .BI(1'b0), .CI(1'b0), .Y(y), .X(x3), .CO(co3));
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endmodule
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EOT
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hierarchy -auto-top
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select -assert-count 3 t:$alu
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arith_tree
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opt_clean
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$alu
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design -reset
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read_verilog -icells <<EOT
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module alu_add5(
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input [11:0] a, b, c, d, e,
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output [11:0] y
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);
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wire [11:0] tmp1, tmp2, tmp3, x1, x2, x3, x4, co1, co2, co3, co4;
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// a + b
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$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
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alu1 (.A(a), .B(b), .BI(1'b0), .CI(1'b0), .Y(tmp1), .X(x1), .CO(co1));
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// c + d
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$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
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alu2 (.A(c), .B(d), .BI(1'b0), .CI(1'b0), .Y(tmp2), .X(x2), .CO(co2));
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// tmp1 + tmp2
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$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
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alu3 (.A(tmp1), .B(tmp2), .BI(1'b0), .CI(1'b0), .Y(tmp3), .X(x3), .CO(co3));
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// tmp3 + e
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$alu #(.A_WIDTH(12), .B_WIDTH(12), .Y_WIDTH(12), .A_SIGNED(0), .B_SIGNED(0))
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alu4 (.A(tmp3), .B(e), .BI(1'b0), .CI(1'b0), .Y(y), .X(x4), .CO(co4));
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endmodule
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EOT
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hierarchy -auto-top
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select -assert-count 4 t:$alu
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arith_tree
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opt_clean
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$alu
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design -reset
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# Test $macc cells (alumacc+opt output)
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read_verilog <<EOT
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module macc_add3(
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input [7:0] a, b, c,
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output [7:0] y
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);
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assign y = a + b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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arith_tree
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opt_clean
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select -assert-count 1 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$macc t:$macc_v2 %u
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design -reset
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read_verilog <<EOT
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module macc_add5(
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input [11:0] a, b, c, d, e,
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output [11:0] y
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);
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assign y = a + b + c + d + e;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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arith_tree
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opt_clean
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$macc t:$macc_v2 %u
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design -reset
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read_verilog <<EOT
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module macc_add8(
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input [15:0] a, b, c, d, e, f, g, h,
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output [15:0] y
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);
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assign y = a + b + c + d + e + f + g + h;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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arith_tree
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opt_clean
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select -assert-count 6 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$macc t:$macc_v2 %u
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design -reset
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107
tests/arith_tree/arith_tree_alu_macc_equiv.ys
Normal file
107
tests/arith_tree/arith_tree_alu_macc_equiv.ys
Normal file
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@ -0,0 +1,107 @@
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read_verilog <<EOT
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module equiv_macc_add3(
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input [3:0] a, b, c,
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output [3:0] y
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);
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assign y = a + b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_macc_add4(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_macc_add8(
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input [3:0] a, b, c, d, e, f, g, h,
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output [3:0] y
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);
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assign y = a + b + c + d + e + f + g + h;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 6 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_macc_signed(
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input signed [3:0] a, b, c, d,
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output signed [5:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_macc_sub_mixed(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a + b - c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module equiv_macc_sub_all(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a - b - c - d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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407
tests/arith_tree/arith_tree_edge_cases.ys
Normal file
407
tests/arith_tree/arith_tree_edge_cases.ys
Normal file
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@ -0,0 +1,407 @@
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read_verilog <<EOT
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module add_1bit(
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input a, b, c,
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output [1:0] y
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);
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assign y = a + b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree
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select -assert-count 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add_1bit_wide(
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input a, b, c, d,
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output [3:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add_wide_out(
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input [7:0] a, b, c, d,
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output [31:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add_mixed(
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input [7:0] a,
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input [3:0] b,
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input [15:0] c,
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input [7:0] d,
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output [15:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add_signed(
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input signed [7:0] a, b, c, d,
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output signed [9:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add_repeated(
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input [7:0] a,
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output [7:0] y
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);
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assign y = a + a + a + a;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add_const(
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input [7:0] a, b, c,
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output [7:0] y
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);
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assign y = a + b + c + 8'd42;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module add_two(
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input [7:0] a, b, c, d, e, f, g, h,
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output [7:0] y1, y2
|
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);
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assign y1 = a + b + c + d;
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assign y2 = e + f + g + h;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree
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select -assert-count 4 t:$fa
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select -assert-count 2 t:$add
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design -reset
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read_verilog <<EOT
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module fir_4tap(
|
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input clk,
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input [15:0] x, c0, c1, c2, c3,
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output reg [31:0] y
|
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);
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reg [15:0] x1, x2, x3;
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always @(posedge clk) begin
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x1 <= x;
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x2 <= x1;
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x3 <= x2;
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end
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wire [31:0] sum = x*c0 + x1*c1 + x2*c2 + x3*c3;
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always @(posedge clk) y <= sum;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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|
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read_verilog <<EOT
|
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module alu_add2(
|
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input [7:0] a, b,
|
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output [7:0] y
|
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);
|
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assign y = a + b;
|
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endmodule
|
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt_clean
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arith_tree
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select -assert-none t:$fa
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select -assert-none t:$add
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select -assert-none t:$sub
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select -assert-count 1 t:$alu
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design -reset
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read_verilog <<EOT
|
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module alu_sub2(
|
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input [7:0] a, b,
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output [7:0] y
|
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);
|
||||
assign y = a - b;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
select -assert-none t:$fa
|
||||
select -assert-none t:$add
|
||||
select -assert-none t:$sub
|
||||
select -assert-count 1 t:$alu
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module alu_compare(
|
||||
input [7:0] a, b,
|
||||
output y
|
||||
);
|
||||
assign y = (a < b);
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
select -assert-none t:$fa
|
||||
select -assert-none t:$add
|
||||
select -assert-none t:$sub
|
||||
select -assert-count 1 t:$alu
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_mul(
|
||||
input [7:0] a, b, c,
|
||||
output [15:0] y
|
||||
);
|
||||
assign y = a * b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-none t:$fa
|
||||
select -assert-min 1 t:$macc t:$macc_v2 %u
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module alu_fanout(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] mid, y
|
||||
);
|
||||
wire [7:0] ab = a + b;
|
||||
assign mid = ab;
|
||||
assign y = ab + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-none t:$fa
|
||||
select -assert-count 2 t:$alu
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_2port(
|
||||
input [7:0] a, b,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-none t:$fa
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_mixed_width(
|
||||
input [7:0] a,
|
||||
input [3:0] b,
|
||||
input [15:0] c,
|
||||
input [7:0] d,
|
||||
output [15:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_signed(
|
||||
input signed [7:0] a, b, c, d,
|
||||
output signed [9:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module fir_4tap_macc(
|
||||
input clk,
|
||||
input [15:0] x, c0, c1, c2, c3,
|
||||
output reg [31:0] y
|
||||
);
|
||||
reg [15:0] x1, x2, x3;
|
||||
always @(posedge clk) begin
|
||||
x1 <= x;
|
||||
x2 <= x1;
|
||||
x3 <= x2;
|
||||
end
|
||||
|
||||
wire [31:0] sum = x*c0 + x1*c1 + x2*c2 + x3*c3;
|
||||
always @(posedge clk) y <= sum;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-min 1 t:$dff
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_mixed_sign(
|
||||
input signed [7:0] a,
|
||||
input [7:0] b,
|
||||
input signed [7:0] c,
|
||||
output signed [9:0] y
|
||||
);
|
||||
assign y = a + b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_wide32(
|
||||
input [31:0] a, b, c, d,
|
||||
output [31:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module passthrough(
|
||||
input [7:0] a,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
select -assert-none t:$fa
|
||||
select -assert-none t:$add
|
||||
select -assert-none t:$sub
|
||||
select -assert-none t:$alu
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_mul_survives(
|
||||
input [7:0] a, b, c, d,
|
||||
output [15:0] y
|
||||
);
|
||||
assign y = a * b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-none t:$fa
|
||||
select -assert-min 1 t:$macc t:$macc_v2 %u
|
||||
design -reset
|
||||
178
tests/arith_tree/arith_tree_equiv.ys
Normal file
178
tests/arith_tree/arith_tree_equiv.ys
Normal file
|
|
@ -0,0 +1,178 @@
|
|||
read_verilog <<EOT
|
||||
module equiv_add3(
|
||||
input [3:0] a, b, c,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a + b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_add4(
|
||||
input [3:0] a, b, c, d,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_add5(
|
||||
input [3:0] a, b, c, d, e,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a + b + c + d + e;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_add8(
|
||||
input [3:0] a, b, c, d, e, f, g, h,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a + b + c + d + e + f + g + h;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 6 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_signed(
|
||||
input signed [3:0] a, b, c, d,
|
||||
output signed [5:0] y
|
||||
);
|
||||
assign y = a + b + c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_mixed(
|
||||
input [1:0] a,
|
||||
input [3:0] b,
|
||||
input [5:0] c,
|
||||
output [5:0] y
|
||||
);
|
||||
assign y = a + b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_sub_3op(
|
||||
input [3:0] a, b, c,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a - b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_sub_mixed(
|
||||
input [3:0] a, b, c, d,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a + b - c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-min 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_sub_all(
|
||||
input [3:0] a, b, c, d,
|
||||
output [3:0] y
|
||||
);
|
||||
assign y = a - b - c - d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-min 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_sub_signed(
|
||||
input signed [3:0] a, b, c, d,
|
||||
output signed [5:0] y
|
||||
);
|
||||
assign y = a + b - c - d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module equiv_double_neg(
|
||||
input [3:0] a, b, c,
|
||||
output [3:0] y
|
||||
);
|
||||
wire [3:0] ab = a - b;
|
||||
assign y = c - ab;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
equiv_opt arith_tree
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
46
tests/arith_tree/arith_tree_idempotent.ys
Normal file
46
tests/arith_tree/arith_tree_idempotent.ys
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
read_verilog <<EOT
|
||||
module add8(
|
||||
input [15:0] a, b, c, d, e, f, g, h,
|
||||
output [15:0] y
|
||||
);
|
||||
assign y = a + b + c + d + e + f + g + h;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
|
||||
arith_tree
|
||||
select -assert-count 6 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
|
||||
arith_tree
|
||||
select -assert-count 6 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_idempotent(
|
||||
input [15:0] a, b, c, d, e, f, g, h,
|
||||
output [15:0] y
|
||||
);
|
||||
assign y = a + b + c + d + e + f + g + h;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
|
||||
arith_tree
|
||||
select -assert-count 6 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$sub
|
||||
select -assert-none t:$alu
|
||||
|
||||
arith_tree
|
||||
select -assert-count 6 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$sub
|
||||
select -assert-none t:$alu
|
||||
design -reset
|
||||
77
tests/arith_tree/arith_tree_negative.ys
Normal file
77
tests/arith_tree/arith_tree_negative.ys
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
read_verilog <<EOT
|
||||
module add2(
|
||||
input [7:0] a, b,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-none t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add_fanout(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] mid, y
|
||||
);
|
||||
wire [7:0] ab = a + b;
|
||||
assign mid = ab;
|
||||
assign y = ab + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-none t:$fa
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module sub2(
|
||||
input [7:0] a, b,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a - b;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-none t:$fa
|
||||
select -assert-count 1 t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add_multi_const(
|
||||
input [7:0] x,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = 8'd1 + 8'd2 + 8'd3 + x;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-none t:$fa
|
||||
select -assert-max 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module add_partial(
|
||||
input [7:0] a, b, c, d, e,
|
||||
output [7:0] mid, y
|
||||
);
|
||||
wire [7:0] ab = a + b;
|
||||
assign mid = ab;
|
||||
assign y = ab + c + d + e;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 2 t:$add
|
||||
design -reset
|
||||
240
tests/arith_tree/arith_tree_sub_chains.ys
Normal file
240
tests/arith_tree/arith_tree_sub_chains.ys
Normal file
|
|
@ -0,0 +1,240 @@
|
|||
read_verilog <<EOT
|
||||
module sub_3op(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a - b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 1 t:$not
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module sub_mixed(
|
||||
input [7:0] a, b, c, d,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b - c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 1 t:$not
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module sub_all(
|
||||
input [7:0] a, b, c, d,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a - b - c - d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 3 t:$not
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module sub_5op(
|
||||
input [11:0] a, b, c, d, e,
|
||||
output [11:0] y
|
||||
);
|
||||
assign y = a - b + c - d + e;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 4 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 2 t:$not
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module sub_signed(
|
||||
input signed [7:0] a, b, c, d,
|
||||
output signed [9:0] y
|
||||
);
|
||||
assign y = a + b - c - d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 2 t:$not
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module sub_double_neg(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] y
|
||||
);
|
||||
wire [7:0] ab = a - b;
|
||||
assign y = c - ab;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
arith_tree
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 1 t:$not
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_sub_3op(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a - b + c;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 2 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_sub_mixed2(
|
||||
input [7:0] a, b, c, d,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b - c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_sub_all(
|
||||
input [7:0] a, b, c, d,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a - b - c - d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_sub_signed(
|
||||
input signed [7:0] a, b, c, d,
|
||||
output signed [9:0] y
|
||||
);
|
||||
assign y = a + b - c - d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt_clean
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-count 3 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-none t:$alu
|
||||
select -assert-none t:$sub
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_sub_mixed(
|
||||
input [7:0] a, b, c, d,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b - c + d;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-none t:$macc t:$macc_v2 %u
|
||||
select -assert-min 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_const(
|
||||
input [7:0] a, b, c,
|
||||
output [7:0] y
|
||||
);
|
||||
assign y = a + b + c + 8'd42;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-none t:$macc t:$macc_v2 %u
|
||||
select -assert-min 1 t:$fa
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
|
||||
read_verilog <<EOT
|
||||
module macc_two(
|
||||
input [7:0] a, b, c, d, e, f, g, h,
|
||||
output [7:0] y1, y2
|
||||
);
|
||||
assign y1 = a + b + c + d;
|
||||
assign y2 = e + f + g + h;
|
||||
endmodule
|
||||
EOT
|
||||
hierarchy -auto-top
|
||||
proc
|
||||
alumacc
|
||||
opt
|
||||
arith_tree
|
||||
opt_clean
|
||||
select -assert-none t:$macc t:$macc_v2 %u
|
||||
select -assert-count 4 t:$fa
|
||||
select -assert-count 2 t:$add
|
||||
design -reset
|
||||
7
tests/arith_tree/run-test.sh
Executable file
7
tests/arith_tree/run-test.sh
Executable file
|
|
@ -0,0 +1,7 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
set -e
|
||||
for x in *.ys; do
|
||||
echo "Running $x.."
|
||||
../../yosys -ql ${x%.ys}.log $x
|
||||
done
|
||||
Loading…
Add table
Add a link
Reference in a new issue