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adffs test update (equiv_opt -multiclock).

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SergeyDegtyar 2019-09-24 14:55:32 +03:00
parent 7e8f7f4c59
commit fc6ebf8268
2 changed files with 13 additions and 18 deletions
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13
tests/ice40/adffs.ys
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@ -1,12 +1,11 @@
read_verilog adffs.v
proc
async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFF
select -assert-count 1 t:SB_DFFN
select -assert-count 2 t:SB_DFFSR
select -assert-count 7 t:SB_LUT4
select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D
select -assert-count 1 t:SB_DFFNSR
select -assert-count 2 t:SB_DFFR
select -assert-count 1 t:SB_DFFSS
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_DFFNSR t:SB_DFFR t:SB_DFFSS t:SB_LUT4 %% t:* %D