mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-09 04:31:25 +00:00
Code Activity

Fixed handling of power operator

Browse source
This commit is contained in:
Clifford Wolf 2013-11-07 22:20:00 +01:00
parent d7cb62ac96
commit fc6dc0d7b8
4 changed files with 79 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

15
tests/simple/constpower.v Normal file
View file

@ -0,0 +1,15 @@
module constpower(ys, yu);
output [8*8*8-1:0] ys, yu;
genvar i, j;
generate
for (i = 0; i < 8; i = i+1)
for (j = 0; j < 8; j = j+1) begin:V
assign ys[i*8 + j*64 + 7 : i*8 + j*64] = $signed(i-4) ** $signed(j-4);
assign yu[i*8 + j*64 + 7 : i*8 + j*64] = $unsigned(i) ** $unsigned(j);
end
endgenerate
endmodule