mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Merge branch 'xaig' into xc7mux

Browse source
This commit is contained in:
Eddie Hung 2019-04-16 13:15:53 -07:00
commit fc5fda595d
2 changed files with 1 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

3
passes/techmap/abc9.cc
View file

@ -414,8 +414,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Selection& sel = design->selection_stack.back();
sel.select(module);
// Adopt same behaviour as abc
// TODO: How to specify don't-care to abc9?
// Behave as for "abc" where BLIF writer implicitly outputs all undef as zero
Pass::call(design, "setundef -zero");
Pass::call(design, "aigmap");

1
tests/simple_abc9/run-test.sh
View file

@ -18,6 +18,5 @@ if ! which iverilog > /dev/null ; then
fi
cp ../simple/*.v .
rm partsel.v # FIXME: Contains 1'hx, thus write_xaiger fails
DOLLAR='?'
exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_'"