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Merge branch 'xaig' into xc7mux

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Eddie Hung 2019-04-16 13:15:53 -07:00
commit fc5fda595d
2 changed files with 1 additions and 3 deletions
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passes/techmap/abc9.cc
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@ -414,8 +414,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Selection& sel = design->selection_stack.back();
sel.select(module);
// Adopt same behaviour as abc
// TODO: How to specify don't-care to abc9?
// Behave as for "abc" where BLIF writer implicitly outputs all undef as zero
Pass::call(design, "setundef -zero");
Pass::call(design, "aigmap");