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lattice: Fix mapping onto DP8KC for data width 1 or 2

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This commit is contained in:
Martin Povišer 2023-12-20 23:23:02 +01:00
parent 112b11116d
commit fc5c5172f8
1 changed files with 14 additions and 2 deletions
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16
techlibs/lattice/brams_map_8kc.v
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@ -38,8 +38,20 @@ endfunction
wire [8:0] DOA;
wire [8:0] DOB;
wire [8:0] DIA = PORT_A_WR_DATA;
wire [8:0] DIB = PORT_B_WR_DATA;
wire [8:0] DIA;
wire [8:0] DIB;
case(PORT_A_WIDTH)
1: assign DIA = {7'bx, PORT_A_WR_DATA[0], 1'bx};
2: assign DIA = {3'bx, PORT_A_WR_DATA[1], 2'bx, PORT_A_WR_DATA[0], 2'bx};
default: assign DIA = PORT_A_WR_DATA;
endcase
case(PORT_B_WIDTH)
1: assign DIB = {7'bx, PORT_B_WR_DATA[0], 1'bx};
2: assign DIB = {3'bx, PORT_B_WR_DATA[1], 2'bx, PORT_B_WR_DATA[0], 2'bx};
default: assign DIB = PORT_B_WR_DATA;
endcase
assign PORT_A_RD_DATA = DOA;
assign PORT_B_RD_DATA = DOB;