From fc2cb32e50f1cb920ae770302c9a90dd5dc251de Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 5 Aug 2025 12:24:05 +1200 Subject: [PATCH] autoname.cc: Avoid int overflow --- passes/cmds/autoname.cc | 67 ++++++++++++++++++++++++++--------------- 1 file changed, 42 insertions(+), 25 deletions(-) diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc index 737bd3e58..75e54f4b1 100644 --- a/passes/cmds/autoname.cc +++ b/passes/cmds/autoname.cc @@ -22,11 +22,24 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -int autoname_worker(Module *module, const dict& wire_score) +typedef struct name_proposal { + string name; + unsigned int score; + name_proposal() : name(""), score(-1) { } + name_proposal(string name, unsigned int score) : name(name), score(score) { } + bool operator<(const name_proposal &other) const { + if (score != other.score) + return score < other.score; + else + return name.length() < other.name.length(); + } +} name_proposal; + +int autoname_worker(Module *module, const dict& wire_score) { - dict> proposed_cell_names; - dict> proposed_wire_names; - int best_score = -1; + dict proposed_cell_names; + dict proposed_wire_names; + name_proposal best_name; for (auto cell : module->selected_cells()) { if (cell->name[0] == '$') { @@ -36,14 +49,14 @@ int autoname_worker(Module *module, const dict& wire_score) if (bit.wire != nullptr && bit.wire->name[0] != '$') { if (suffix.empty()) suffix = stringf("_%s_%s", log_id(cell->type), log_id(conn.first)); - string new_name(bit.wire->name.str() + suffix); - int score = wire_score.at(bit.wire); - if (cell->output(conn.first)) score = 0; - score = 10000*score + new_name.size(); - if (!proposed_cell_names.count(cell) || score < proposed_cell_names.at(cell).first) { - if (best_score < 0 || score < best_score) - best_score = score; - proposed_cell_names[cell] = make_pair(score, new_name); + name_proposal proposed_name( + bit.wire->name.str() + suffix, + cell->output(conn.first) ? 0 : wire_score.at(bit.wire) + ); + if (!proposed_cell_names.count(cell) || proposed_name < proposed_cell_names.at(cell)) { + if (proposed_name < best_name) + best_name = proposed_name; + proposed_cell_names[cell] = proposed_name; } } } @@ -54,32 +67,36 @@ int autoname_worker(Module *module, const dict& wire_score) if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) { if (suffix.empty()) suffix = stringf("_%s", log_id(conn.first)); - string new_name(cell->name.str() + suffix); - int score = wire_score.at(bit.wire); - if (cell->output(conn.first)) score = 0; - score = 10000*score + new_name.size(); - if (!proposed_wire_names.count(bit.wire) || score < proposed_wire_names.at(bit.wire).first) { - if (best_score < 0 || score < best_score) - best_score = score; - proposed_wire_names[bit.wire] = make_pair(score, new_name); + name_proposal proposed_name( + cell->name.str() + suffix, + cell->output(conn.first) ? 0 : wire_score.at(bit.wire) + ); + if (!proposed_wire_names.count(bit.wire) || proposed_name < proposed_wire_names.at(bit.wire)) { + if (proposed_name < best_name) + best_name = proposed_name; + proposed_wire_names[bit.wire] = proposed_name; } } } } } + // compare against double best score for following comparisons so we don't + // pre-empt a future iteration + best_name.score *= 2; + for (auto &it : proposed_cell_names) { - if (best_score*2 < it.second.first) + if (best_name < it.second) continue; - IdString n = module->uniquify(IdString(it.second.second)); + IdString n = module->uniquify(IdString(it.second.name)); log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); module->rename(it.first, n); } for (auto &it : proposed_wire_names) { - if (best_score*2 < it.second.first) + if (best_name < it.second) continue; - IdString n = module->uniquify(IdString(it.second.second)); + IdString n = module->uniquify(IdString(it.second.name)); log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); module->rename(it.first, n); } @@ -115,7 +132,7 @@ struct AutonamePass : public Pass { for (auto module : design->selected_modules()) { - dict wire_score; + dict wire_score; for (auto cell : module->selected_cells()) for (auto &conn : cell->connections()) for (auto bit : conn.second)