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Progress in Verific bindings

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This commit is contained in:
Clifford Wolf 2014-03-15 15:31:54 +01:00
parent 1d00ad9d4d
commit fc2c821407
1 changed files with 15 additions and 7 deletions
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22
frontends/verific/verific.cc
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@ -249,9 +249,9 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
if (inst->GetCout() != NULL) if (inst->GetCout() != NULL)
out.append(net_map.at(inst->GetCout())); out.append(net_map.at(inst->GetCout()));
if (const_map.count(inst->GetCin()) && const_map.at(inst->GetCin()) == RTLIL::State::S0) { if (const_map.count(inst->GetCin()) && const_map.at(inst->GetCin()) == RTLIL::State::S0) {
module->addAdd(RTLIL::escape_id(inst->Name()) + "_", IN1, IN2, out, SIGNED); module->addAdd(RTLIL::escape_id(inst->Name()), IN1, IN2, out, SIGNED);
} else { } else {
RTLIL::SigSpec tmp = module->new_wire(inst->OutputSize(), NEW_ID); RTLIL::SigSpec tmp = module->new_wire(out.width, NEW_ID);
module->addAdd(NEW_ID, IN1, IN2, tmp, SIGNED); module->addAdd(NEW_ID, IN1, IN2, tmp, SIGNED);
module->addAdd(RTLIL::escape_id(inst->Name()), tmp, net_map.at(inst->GetCin()), out, false); module->addAdd(RTLIL::escape_id(inst->Name()), tmp, net_map.at(inst->GetCin()), out, false);
} }
@ -278,6 +278,9 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
return true; return true;
} }
#if 0
// FIXME: tests/simple/sincos.v exposes a bug in this operator
if (inst->Type() == OPER_SHIFT_LEFT) { if (inst->Type() == OPER_SHIFT_LEFT) {
module->addShl(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED); module->addShl(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
return true; return true;
@ -287,6 +290,7 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
module->addShr(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED); module->addShr(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
return true; return true;
} }
#endif
if (inst->Type() == OPER_REDUCE_AND) { if (inst->Type() == OPER_REDUCE_AND) {
module->addReduceAnd(RTLIL::escape_id(inst->Name()), IN, net_map.at(inst->GetOutput()), SIGNED); module->addReduceAnd(RTLIL::escape_id(inst->Name()), IN, net_map.at(inst->GetOutput()), SIGNED);
@ -322,10 +326,14 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
return true; return true;
} }
#if 0
// FIXME: tests/simple/sincos.v exposes a bug in this operator
if (inst->Type() == OPER_LESSTHAN) { if (inst->Type() == OPER_LESSTHAN) {
module->addLt(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED); module->addLt(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
return true; return true;
} }
#endif
if (inst->Type() == OPER_WIDE_AND) { if (inst->Type() == OPER_WIDE_AND) {
module->addAnd(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED); module->addAnd(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED);
@ -382,12 +390,12 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
} }
if (inst->Type() == OPER_EQUAL) { if (inst->Type() == OPER_EQUAL) {
module->addEq(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED); module->addEq(RTLIL::escape_id(inst->Name()), IN1, IN2, net_map.at(inst->GetOutput()), SIGNED);
return true; return true;
} }
if (inst->Type() == OPER_NEQUAL) { if (inst->Type() == OPER_NEQUAL) {
module->addNe(RTLIL::escape_id(inst->Name()), IN1, IN2, OUT, SIGNED); module->addNe(RTLIL::escape_id(inst->Name()), IN1, IN2, net_map.at(inst->GetOutput()), SIGNED);
return true; return true;
} }
@ -567,13 +575,13 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
const_map[inst->GetOutput()] = RTLIL::State::S1; const_map[inst->GetOutput()] = RTLIL::State::S1;
if (inst->Type() == PRIM_GND) if (inst->Type() == PRIM_GND)
const_map[inst->GetOutput()] = RTLIL::State::S1; const_map[inst->GetOutput()] = RTLIL::State::S0;
if (inst->Type() == PRIM_X) if (inst->Type() == PRIM_X)
const_map[inst->GetOutput()] = RTLIL::State::S1; const_map[inst->GetOutput()] = RTLIL::State::Sx;
if (inst->Type() == PRIM_Z) if (inst->Type() == PRIM_Z)
const_map[inst->GetOutput()] = RTLIL::State::S1; const_map[inst->GetOutput()] = RTLIL::State::Sz;
} }
FOREACH_INSTANCE_OF_NETLIST(nl, mi, inst) FOREACH_INSTANCE_OF_NETLIST(nl, mi, inst)