mirror of
https://github.com/YosysHQ/yosys
synced 2025-09-06 01:48:06 +00:00
Update cells supported for verilog to FIRRTL conversion.
Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
This commit is contained in:
parent
807b3c7697
commit
fc1c9aa11f
5 changed files with 317 additions and 55 deletions
|
@ -1,7 +1,7 @@
|
|||
|
||||
EXTRA_FLAGS=
|
||||
SEED=
|
||||
|
||||
# Don't bother defining default values for SEED and EXTRA_FLAGS.
|
||||
# Their "natural" default values should be sufficient,
|
||||
# and they may be overridden in the environment.
|
||||
ifneq ($(strip $(SEED)),)
|
||||
SEEDOPT=-S$(SEED)
|
||||
endif
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue