mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Added blackbox $__COUNT_ cell model

Browse source
This commit is contained in:
Andrew Zonenberg 2017-08-29 14:17:29 -07:00
parent 80aaf50302
commit fc0c7f74dc
2 changed files with 18 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
techlibs/greenpak4/Makefile.inc
View file

@ -2,6 +2,7 @@
OBJS += techlibs/greenpak4/synth_greenpak4.o OBJS += techlibs/greenpak4/synth_greenpak4.o
OBJS += techlibs/greenpak4/greenpak4_dffinv.o OBJS += techlibs/greenpak4/greenpak4_dffinv.o
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_blackbox.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_latch.v)) $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_latch.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v)) $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v)) $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v))

17
techlibs/greenpak4/cells_blackbox.v Normal file
View file

@ -0,0 +1,17 @@
module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
input wire CE;
input wire CLK;
output reg OUT;
output reg[WIDTH-1:0] POUT;
input wire RST;
input wire UP;
parameter COUNT_TO = 1;
parameter RESET_MODE = "RISING";
parameter HAS_POUT = 0;
parameter HAS_CE = 0;
parameter WIDTH = 8;
parameter DIRECTION = "DOWN";
endmodule