From fbdfff168b4d2361ef98ca21c186cb81b12ca539 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 17 Jun 2024 10:53:08 +0200 Subject: [PATCH] placement new, fix empty probably --- kernel/rtlil.cc | 139 +++++++++++++++++++++++++++++++++++++++++++++--- kernel/rtlil.h | 7 ++- 2 files changed, 138 insertions(+), 8 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 2aa0c5b1d..65b675184 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2427,15 +2427,26 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *oth RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) { RTLIL::Cell *cell = new RTLIL::Cell; - // std::cout << "alloc " << (long long)cell << " called " << cell->name.c_str() << "\n"; - cell->module = this; + std::cout << "RTLIL::Module::addCell " << name.c_str() << " " << type.c_str() << "to module " << this->name.c_str() << "\n"; + log("ptr 0x%016X\n", cell); cell->name = name; cell->type = type; if (RTLIL::Cell::is_legacy_type(type)) { - std::cout << "new RTLIL::OldCell\n"; cell->legacy = new RTLIL::OldCell; cell->legacy->name = name; cell->legacy->type = type; + cell->legacy->module = this; + log_assert(this); + } else { + // Due to the tagged union deal, + // we don't get this automagically, + // so let's use "placement new" + for (auto param: cell->parameters) { + new (¶m.second) Const(); + } + for (auto conn: cell->connections_) { + new (&conn.second) SigSpec(); + } } add(cell); return cell; @@ -2448,7 +2459,6 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth cell->connections_ = other->connections_; cell->parameters = other->parameters; cell->attributes = other->attributes; - add(cell); return cell; } @@ -3508,10 +3518,27 @@ void RTLIL::Cell::setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal } else { throw std::out_of_range("Cell::setPort()"); } + } else if (type == ID($pos)) { + if (portname == ID::A) { + pos.a = signal; + } else if (portname == ID::Y) { + pos.y = signal; + } else { + throw std::out_of_range("Cell::setPort()"); + } + } else if (type == ID($neg)) { + if (portname == ID::A) { + neg.a = signal; + } else if (portname == ID::Y) { + neg.y = signal; + } else { + throw std::out_of_range("Cell::setPort()"); + } } else { throw std::out_of_range("Cell::setPort()"); } } + const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) const { if (is_legacy()) return legacy->getPort(portname); @@ -3524,6 +3551,22 @@ const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString &portname) cons } else { throw std::out_of_range("Cell::setPort()"); } + } else if (type == ID($pos)) { + if (portname == ID::A) { + return pos.a; + } else if (portname == ID::Y) { + return pos.y; + } else { + throw std::out_of_range("Cell::setPort()"); + } + } else if (type == ID($neg)) { + if (portname == ID::A) { + return neg.a; + } else if (portname == ID::Y) { + return neg.y; + } else { + throw std::out_of_range("Cell::setPort()"); + } } else { throw std::out_of_range("Cell::setPort()"); } @@ -3540,6 +3583,22 @@ RTLIL::SigSpec &RTLIL::Cell::getMutPort(const RTLIL::IdString &portname) { } else { throw std::out_of_range("Cell::setPort()"); } + } else if (type == ID($pos)) { + if (portname == ID::A) { + return pos.a; + } else if (portname == ID::Y) { + return pos.y; + } else { + throw std::out_of_range("Cell::setPort()"); + } + } else if (type == ID($neg)) { + if (portname == ID::A) { + return neg.a; + } else if (portname == ID::Y) { + return neg.y; + } else { + throw std::out_of_range("Cell::setPort()"); + } } else { throw std::out_of_range("Cell::setPort()"); } @@ -3557,6 +3616,28 @@ void RTLIL::Cell::setParam(const RTLIL::IdString ¶mname, RTLIL::Const value) not_.a_width = value.as_int(); } else if (paramname == ID::Y_WIDTH) { not_.y_width = value.as_int(); + } else if (paramname == ID::A_SIGNED) { + not_.is_signed = value.as_int(); + } else { + throw std::out_of_range("Cell::setParam()"); + } + } else if (type == ID($pos)) { + if (paramname == ID::A_WIDTH) { + pos.a_width = value.as_int(); + } else if (paramname == ID::Y_WIDTH) { + pos.y_width = value.as_int(); + } else if (paramname == ID::A_SIGNED) { + pos.is_signed = value.as_int(); + } else { + throw std::out_of_range("Cell::setParam()"); + } + } else if (type == ID($neg)) { + if (paramname == ID::A_WIDTH) { + neg.a_width = value.as_int(); + } else if (paramname == ID::Y_WIDTH) { + neg.y_width = value.as_int(); + } else if (paramname == ID::A_SIGNED) { + neg.is_signed = value.as_int(); } else { throw std::out_of_range("Cell::setParam()"); } @@ -3566,14 +3647,38 @@ void RTLIL::Cell::setParam(const RTLIL::IdString ¶mname, RTLIL::Const value) } const RTLIL::Const& RTLIL::Cell::getParam(const RTLIL::IdString ¶mname) const { + log_debug("paramname %s, type %s\n", paramname.c_str(), type.c_str()); if (is_legacy()) return legacy->getParam(paramname); + log_debug("fr"); if (type == ID($not)) { if (paramname == ID::A_WIDTH) { return not_.a_width; } else if (paramname == ID::Y_WIDTH) { return not_.y_width; + } else if (paramname == ID::A_SIGNED) { + return not_.is_signed; + } else { + throw std::out_of_range("Cell::getParam()"); + } + } else if (type == ID($pos)) { + if (paramname == ID::A_WIDTH) { + return pos.a_width; + } else if (paramname == ID::Y_WIDTH) { + return pos.y_width; + } else if (paramname == ID::A_SIGNED) { + return pos.is_signed; + } else { + throw std::out_of_range("Cell::getParam()"); + } + } else if (type == ID($neg)) { + if (paramname == ID::A_WIDTH) { + return neg.a_width; + } else if (paramname == ID::Y_WIDTH) { + return neg.y_width; + } else if (paramname == ID::A_SIGNED) { + return neg.is_signed; } else { throw std::out_of_range("Cell::getParam()"); } @@ -3591,11 +3696,33 @@ RTLIL::Const& RTLIL::Cell::getMutParam(const RTLIL::IdString ¶mname) { return not_.a_width; } else if (paramname == ID::Y_WIDTH) { return not_.y_width; + } else if (paramname == ID::A_SIGNED) { + return not_.is_signed; } else { - throw std::out_of_range("Cell::getParam()"); + throw std::out_of_range("Cell::getMutParam()"); + } + } else if (type == ID($pos)) { + if (paramname == ID::A_WIDTH) { + return pos.a_width; + } else if (paramname == ID::Y_WIDTH) { + return pos.y_width; + } else if (paramname == ID::A_SIGNED) { + return pos.is_signed; + } else { + throw std::out_of_range("Cell::getMutParam()"); + } + } else if (type == ID($neg)) { + if (paramname == ID::A_WIDTH) { + return neg.a_width; + } else if (paramname == ID::Y_WIDTH) { + return neg.y_width; + } else if (paramname == ID::A_SIGNED) { + return neg.is_signed; + } else { + throw std::out_of_range("Cell::getMutParam()"); } } else { - throw std::out_of_range("Cell::getParam()"); + throw std::out_of_range("Cell::getMutParam()"); } } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 0b79b27b1..986cc0962 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1721,6 +1721,7 @@ public: // but we rely on RTLIL::Cell always being constructed correctly // since its layout is fixed as defined by InternalOldCellChecker RTLIL::Const& operator[](RTLIL::IdString name) { + log("operator[] on %s type %s\n", name.c_str(), parent->type.c_str()); return parent->getMutParam(name); } void operator=(dict from) { @@ -1965,6 +1966,7 @@ public: // but we rely on RTLIL::Cell always being constructed correctly // since its layout is fixed as defined by InternalOldCellChecker RTLIL::SigSpec& operator[](RTLIL::IdString portname) { + log("operator[] on %s type %s\n", portname.c_str(), parent->type.c_str()); return parent->getMutPort(portname); } void operator=(dict from) { @@ -2225,7 +2227,8 @@ public: const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const; RTLIL::SigSpec &getMutPort(const RTLIL::IdString &portname); bool hasPort(const RTLIL::IdString &portname) const { - return connections_.count(portname); + // TODO hack? + return connections_.count(portname) && !getPort(portname).empty(); } // The need for this function implies setPort will be used on incompat types void unsetPort(const RTLIL::IdString& portname) { (void)portname; } @@ -2234,7 +2237,7 @@ public: const RTLIL::Const& getParam(const RTLIL::IdString ¶mname) const; RTLIL::Const& getMutParam(const RTLIL::IdString ¶mname); bool hasParam(const RTLIL::IdString ¶mname) const { - return parameters.count(paramname); + return parameters.count(paramname) && !getParam(paramname).empty(); } // The need for this function implies setPort will be used on incompat types void unsetParam(const RTLIL::IdString& paramname) { (void)paramname; }