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Revert some stuff

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This commit is contained in:
Akash Levy 2025-09-29 00:43:49 -07:00
parent 0b0c7bd19d
commit fbc2b71ed4
9 changed files with 8 additions and 42 deletions
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13
kernel/cost.cc
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@ -102,13 +102,6 @@ static bool is_free(RTLIL::IdString type)
type.in(ID($specrule), ID($specify2), ID($specify3)));
}
static bool is_mem(RTLIL::IdString type)
{
return (
// tags
type.in(ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2)));
}
unsigned int max_inp_width(RTLIL::Cell *cell)
{
unsigned int max = 0;
@ -213,13 +206,9 @@ unsigned int CellCosts::get(RTLIL::Cell *cell)
} else if (is_free(cell->type)) {
log_debug("%s is free\n", cell->name);
return 0;
} else if (is_mem(cell->type)) {
// SILIMATE: Memory cells have no bearing on cross module optimizations
log_debug("%s is mem\n", cell->name.c_str());
return 1;
}
// TODO: $fsm
// ignored: $pow
// ignored: $pow $memrd $memwr $meminit (and v2 counterparts)
log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters));
return 1;

6
kernel/modtools.h
View file

@ -78,7 +78,6 @@ struct ModIndex : public RTLIL::Monitor
SigMap sigmap;
RTLIL::Module *module;
std::map<RTLIL::SigBit, SigBitInfo> database;
int reload_counter;
int auto_reload_counter;
bool auto_reload_module;
@ -107,10 +106,6 @@ struct ModIndex : public RTLIL::Monitor
void reload_module(bool reset_sigmap = true)
{
reload_counter++;
if (reload_counter % 10 == 0)
log_warning("ModIndex::reload_module() called %d times.\n", reload_counter);
if (reset_sigmap) {
sigmap.clear();
sigmap.set(module);
@ -236,7 +231,6 @@ struct ModIndex : public RTLIL::Monitor
ModIndex(RTLIL::Module *_m) : sigmap(_m), module(_m)
{
reload_counter = 0;
auto_reload_counter = 0;
auto_reload_module = true;
module->monitors.insert(this);

12
kernel/rtlil.cc
View file

@ -5437,18 +5437,6 @@ bool RTLIL::SigSpec::is_chunk() const
return GetSize(chunks_) == 1;
}
bool RTLIL::SigSpec::is_mostly_const() const
{
cover("kernel.rtlil.sigspec.is_mostly_const");
pack();
int constbits = 0;
for (auto it = chunks_.begin(); it != chunks_.end(); it++)
if (it->width > 0 && it->wire == NULL)
constbits += it->width;
return (constbits > width_/2);
}
bool RTLIL::SigSpec::known_driver() const
{
pack();

2
kernel/rtlil.h
View file

@ -1346,8 +1346,6 @@ public:
bool is_chunk() const;
inline bool is_bit() const { return width_ == 1; }
bool is_mostly_const() const;
bool known_driver() const;
bool is_fully_const() const;