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Release version 0.32

This commit is contained in:
Miodrag Milanovic 2023-08-07 08:22:52 +02:00
parent e0ba07aed3
commit fbab08acf1
2 changed files with 10 additions and 3 deletions

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@ -2,8 +2,15 @@
List of major changes and improvements between releases
=======================================================
Yosys 0.31 .. Yosys 0.32-dev
Yosys 0.31 .. Yosys 0.32
--------------------------
* Verific support
- Added sub option "-lib" to reading commands for VHDL and
SystemVerilog, that will later import all units/modules from
marked files as blackboxes.
* Various
- Added support for $lt, $le, $gt, $ge to the code generating AIGs.
Yosys 0.30 .. Yosys 0.31
--------------------------