mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 19:05:52 +00:00
Code Activity

New behavior for front-end handling of whiteboxes

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-04-20 22:24:50 +02:00
parent f84a84e3f1
commit fb7f02be55
6 changed files with 103 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

3
README.md
View file

@ -316,6 +316,9 @@ Verilog Attributes and non-standard features
``blackbox``, but is for whitebox modules, i.e. library modules that
contain a behavioral model of the cell type.
- The ``lib_whitebox`` attribute overwrites ``whitebox`` when ``read_verilog``
is run in `-lib` mode. Otherwise it's automatically removed.
- The ``dynports`` attribute is used by the Verilog front-end to mark modules
that have ports with a width that depends on a parameter.