3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-08 20:21:25 +00:00

ice40: move over to specify blocks for -abc9

This commit is contained in:
Eddie Hung 2020-02-13 09:58:20 -08:00
parent a85c55113f
commit fb60d82971
10 changed files with 1344 additions and 164 deletions

View file

@ -245,7 +245,7 @@ struct SynthIce40Pass : public ScriptPass
define = "-D ICE40_U";
else
define = "-D ICE40_HX";
run("read_verilog " + define + " -lib +/ice40/cells_sim.v");
run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc");
}
@ -352,7 +352,7 @@ struct SynthIce40Pass : public ScriptPass
}
if (!noabc) {
if (abc9) {
run("read_verilog -icells -lib +/ice40/abc9_model.v");
run("read_verilog -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
int wire_delay;
if (device_opt == "lp")
wire_delay = 400;
@ -360,7 +360,7 @@ struct SynthIce40Pass : public ScriptPass
wire_delay = 750;
else
wire_delay = 250;
run(stringf("abc9 -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()));
run(stringf("abc9 -W %d", wire_delay, device_opt.c_str(), device_opt.c_str()));
}
else
run("abc -dress -lut 4", "(skip if -noabc)");