From e20a57b09ed3efd79fd893035c8f70747e5b3efa Mon Sep 17 00:00:00 2001 From: Mike Inouye Date: Wed, 13 May 2026 10:57:18 -0700 Subject: [PATCH 01/30] Reuse knowledge_t and pass by reference --- passes/opt/opt_muxtree.cc | 56 ++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 8bf151e71..4c07f61d8 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -200,6 +200,29 @@ struct OptMuxtreeWorker root_muxes.at(driving_mux) = true; } + struct knowledge_t + { + // Known inactive signals + // The payload is a reference counter used to manage the list + // When it is non-zero, the signal in known to be inactive + // When it reaches zero, the map element is removed + std::vector known_inactive; + + // database of known active signals + std::vector known_active; + + // this is just used to keep track of visited muxes in order to prohibit + // endless recursion in mux loops + std::vector visited_muxes; + + // Initialize with the maximum possible sizes + knowledge_t(int num_bits, int num_muxes) { + known_inactive.assign(num_bits, 0); + known_active.assign(num_bits, 0); + visited_muxes.assign(num_muxes, false); + } + }; + OptMuxtreeWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module), assign_map(module), removed_count(0) { @@ -227,11 +250,13 @@ struct OptMuxtreeWorker populate_roots(); + knowledge_t shared_knowledge(GetSize(bit2info), GetSize(mux2info)); + for (int mux_idx = 0; mux_idx < GetSize(root_muxes); mux_idx++) if (root_muxes.at(mux_idx)) { log_debug(" Root of a mux tree: %s%s\n", log_id(mux2info[mux_idx].cell), root_enable_muxes.at(mux_idx) ? " (pure)" : ""); root_mux_rerun.erase(mux_idx); - eval_root_mux(mux_idx); + eval_root_mux(shared_knowledge, mux_idx); if (glob_evals_left == 0) { log(" Giving up (too many iterations)\n"); return; @@ -243,7 +268,7 @@ struct OptMuxtreeWorker log_debug(" Root of a mux tree: %s (rerun as non-pure)\n", log_id(mux2info[mux_idx].cell)); log_assert(root_enable_muxes.at(mux_idx)); root_mux_rerun.erase(mux_idx); - eval_root_mux(mux_idx); + eval_root_mux(shared_knowledge, mux_idx); if (glob_evals_left == 0) { log(" Giving up (too many iterations)\n"); return; @@ -334,29 +359,6 @@ struct OptMuxtreeWorker return results; } - struct knowledge_t - { - // Known inactive signals - // The payload is a reference counter used to manage the list - // When it is non-zero, the signal in known to be inactive - // When it reaches zero, the map element is removed - std::vector known_inactive; - - // database of known active signals - std::vector known_active; - - // this is just used to keep track of visited muxes in order to prohibit - // endless recursion in mux loops - std::vector visited_muxes; - - // Initialize with the maximum possible sizes - knowledge_t(int num_bits, int num_muxes) { - known_inactive.assign(num_bits, 0); - known_active.assign(num_bits, 0); - visited_muxes.assign(num_muxes, false); - } - }; - static void activate_port(knowledge_t &knowledge, int port_idx, const muxinfo_t &muxinfo) { // First, mark all other ports inactive for (int i = 0; i < GetSize(muxinfo.ports); i++) { @@ -579,14 +581,14 @@ struct OptMuxtreeWorker } } - void eval_root_mux(int mux_idx) + void eval_root_mux(knowledge_t &knowledge, int mux_idx) { log_assert(glob_evals_left > 0); - knowledge_t knowledge(GetSize(bit2info), GetSize(mux2info)); knowledge.visited_muxes[mux_idx] = true; limits_t limits = {}; limits.do_mark_ports_observable = root_enable_muxes.at(mux_idx); eval_mux(knowledge, mux_idx, limits); + knowledge.visited_muxes[mux_idx] = false; } }; From 6ac8758e7eb42ca498b4dfa93672335344e920e5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 7 May 2026 09:44:42 +0200 Subject: [PATCH 02/30] Generate coverage for tests --- .github/workflows/test-verific.yml | 26 +++++++++++++++++++++++++- Makefile | 1 + 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index 132aac589..6e3284167 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -47,7 +47,7 @@ jobs: - name: Build Yosys run: | - make config-clang + make config-gcov echo "ENABLE_VERIFIC := 1" >> Makefile.conf echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf @@ -85,6 +85,30 @@ jobs: run: | make -C sby run_ci + - name: Run coverage + if: ${{ github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch' }} + run: | + make coverage + + - name: Push coverage + if: ${{ github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch' }} + run: | + git clone https://x-access-token:${{ secrets.REPORTS_TOKEN }}@github.com/YosysHQ/reports.git out + rm -rf out/coverage/main + mkdir -p out/coverage/main + cp -r coverage_html/* out/coverage/main/ + cd out + # find . -name "*.html" -type f -print0 | xargs -0 sed -i -z 's#\(Date:[[:space:]]*\)[^<]*\(\)#\1\2#g' + git config user.name "yosyshq-ci" + git config user.email "105224853+yosyshq-ci@users.noreply.github.com" + git add . + if ! git diff --cached --quiet; then + git commit -m "Update coverage" + git push + else + echo "No changes to commit" + fi + test-pyosys: needs: pre_job if: ${{ needs.pre_job.outputs.should_skip != 'true' && github.repository_owner == 'YosysHQ' }} diff --git a/Makefile b/Makefile index 3c5c10cda..f6ba73375 100644 --- a/Makefile +++ b/Makefile @@ -1117,6 +1117,7 @@ coverage: ./$(PROGRAM_PREFIX)yosys -qp 'help; help -all' rm -rf coverage.info coverage_html lcov --capture -d . --no-external -o coverage.info + lcov --remove coverage.info '*/tests/various/*' '*/libs/*' -o coverage.info --ignore-errors unused genhtml coverage.info --output-directory coverage_html clean_coverage: From 8022b5445b5967ea7fd2065629d3574861a099c8 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 15 May 2026 11:59:22 +0200 Subject: [PATCH 03/30] Convert to using LLVM code coverage --- .github/workflows/test-verific.yml | 9 +++++++++ .gitignore | 4 ++-- Makefile | 19 +++++++++++-------- 3 files changed, 22 insertions(+), 10 deletions(-) diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index 6e3284167..bdd35428a 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -44,6 +44,14 @@ jobs: - name: Runtime environment run: | echo "procs=$(nproc)" >> $GITHUB_ENV + mkdir -p "${GITHUB_WORKSPACE}/coverage" + echo "LLVM_PROFILE_FILE=${GITHUB_WORKSPACE}/coverage/coverage_%p.profraw" >> $GITHUB_ENV + echo "LLVM_PROFILE_FILE_BUFFER_SIZE=0" >> $GITHUB_ENV + + - name: Skip generating files + if: ${{ github.event_name != 'merge_group' && github.event_name != 'workflow_dispatch' }} + run: | + echo "LLVM_PROFILE_FILE=/dev/null" >> $GITHUB_ENV - name: Build Yosys run: | @@ -89,6 +97,7 @@ jobs: if: ${{ github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch' }} run: | make coverage + make clean_coverage - name: Push coverage if: ${{ github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch' }} diff --git a/.gitignore b/.gitignore index a8b04ac45..b39088088 100644 --- a/.gitignore +++ b/.gitignore @@ -65,10 +65,10 @@ /viz.js # other -/coverage.info +/yosys.profdata +/coverage /coverage_html - # these really belong in global gitignore since they're not specific to this project but rather to user tool choice # but too many people don't have a global gitignore configured: # https://docs.github.com/en/get-started/git-basics/ignoring-files#configuring-ignored-files-for-all-repositories-on-your-computer diff --git a/Makefile b/Makefile index f6ba73375..3c9911c1c 100644 --- a/Makefile +++ b/Makefile @@ -456,8 +456,11 @@ endif endif ifeq ($(ENABLE_GCOV),1) -CXXFLAGS += --coverage -LINKFLAGS += --coverage +LLVM_PROFILE_FILE ?= $(realpath $(YOSYS_SRC))/coverage/coverage_%p.profraw +export LLVM_PROFILE_FILE +export LLVM_PROFILE_FILE_BUFFER_SIZE=0 +CXXFLAGS += -fprofile-instr-generate -fcoverage-mapping +LINKFLAGS+= -fprofile-instr-generate endif ifeq ($(ENABLE_GPROF),1) @@ -1115,13 +1118,13 @@ mrproper: clean coverage: ./$(PROGRAM_PREFIX)yosys -qp 'help; help -all' - rm -rf coverage.info coverage_html - lcov --capture -d . --no-external -o coverage.info - lcov --remove coverage.info '*/tests/various/*' '*/libs/*' -o coverage.info --ignore-errors unused - genhtml coverage.info --output-directory coverage_html + rm -rf coverage_html + llvm-profdata merge -sparse coverage/coverage_*.profraw -o yosys.profdata + llvm-cov show ./$(PROGRAM_PREFIX)yosys -instr-profile=yosys.profdata -format=html -output-dir=coverage_html --compilation-dir=. -ignore-filename-regex='(^|.*/)Verific/.*|(^|.*/)libs/.*' clean_coverage: - find . -name "*.gcda" -type f -delete + rm -rf coverage + rm -f yosys.profdata FUNC_KERNEL := functional.cc functional.h sexpr.cc sexpr.h compute_graph.h FUNC_INCLUDES := $(addprefix --include *,functional/* $(FUNC_KERNEL)) @@ -1183,7 +1186,7 @@ config-msys2-64: clean echo "PREFIX := $(MINGW_PREFIX)" >> Makefile.conf config-gcov: clean - echo 'CONFIG := gcc' > Makefile.conf + echo 'CONFIG := clang' > Makefile.conf echo 'ENABLE_GCOV := 1' >> Makefile.conf echo 'ENABLE_DEBUG := 1' >> Makefile.conf From 992eceaaa08ceb4a82e83f2ab286a05ea2057736 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 15 May 2026 12:53:04 +0200 Subject: [PATCH 04/30] Ignore configured location --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 3c9911c1c..6fb79624f 100644 --- a/Makefile +++ b/Makefile @@ -1120,7 +1120,7 @@ coverage: ./$(PROGRAM_PREFIX)yosys -qp 'help; help -all' rm -rf coverage_html llvm-profdata merge -sparse coverage/coverage_*.profraw -o yosys.profdata - llvm-cov show ./$(PROGRAM_PREFIX)yosys -instr-profile=yosys.profdata -format=html -output-dir=coverage_html --compilation-dir=. -ignore-filename-regex='(^|.*/)Verific/.*|(^|.*/)libs/.*' + llvm-cov show ./$(PROGRAM_PREFIX)yosys -instr-profile=yosys.profdata -format=html -output-dir=coverage_html --compilation-dir=. -ignore-filename-regex='(^|.*/)libs/.*|/usr/include/.*|$(subst /,\/,$(VERIFIC_DIR))/.*' clean_coverage: rm -rf coverage From 59c1bc35cbad3b50ef29ec48e443ddffafa6a931 Mon Sep 17 00:00:00 2001 From: Leon White Date: Sat, 16 May 2026 09:12:20 +0200 Subject: [PATCH 05/30] Fix aiger tests when ABCEXTERNAL is set --- tests/aiger/generate_mk.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/tests/aiger/generate_mk.py b/tests/aiger/generate_mk.py index a90a63527..e6f3f4091 100644 --- a/tests/aiger/generate_mk.py +++ b/tests/aiger/generate_mk.py @@ -54,6 +54,13 @@ def create_tests(): "rm -f aigmap.err" ])) -extra = [ f"ABC ?= {gen_tests_makefile.yosys_basedir}/yosys-abc", "SHELL := /usr/bin/env bash" ] +extra = [ + "ifneq ($(ABCEXTERNAL),)", + "ABC ?= $(ABCEXTERNAL)", + "else", + f"ABC ?= {gen_tests_makefile.yosys_basedir}/yosys-abc", + "endif", + "SHELL := /usr/bin/env bash", +] gen_tests_makefile.generate_custom(create_tests, extra) From 8bbc3c359cb28024a10c4ecaa1767057bcbaed82 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 15 May 2026 15:16:09 +0200 Subject: [PATCH 06/30] Remove id2cstr uses in our code base --- backends/cxxrtl/cxxrtl_backend.cc | 2 +- .../source/code_examples/stubnets/stubnets.cc | 6 ++-- frontends/verific/verific.cc | 4 +-- kernel/rtlil.cc | 6 ++-- passes/cmds/scc.cc | 6 ++-- passes/cmds/select.cc | 18 ++++++------ passes/cmds/test_select.cc | 4 +-- passes/equiv/equiv_make.cc | 4 +-- passes/fsm/fsm_detect.cc | 2 +- passes/hierarchy/hierarchy.cc | 28 +++++++++---------- passes/sat/cutpoint.cc | 4 +-- passes/sat/expose.cc | 18 ++++++------ passes/sat/freduce.cc | 10 +++---- passes/sat/miter.cc | 2 +- passes/techmap/iopadmap.cc | 14 +++++----- techlibs/ice40/ice40_braminit.cc | 2 +- 16 files changed, 64 insertions(+), 66 deletions(-) diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 3ebe62b90..ac69bda27 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -3420,7 +3420,7 @@ struct CxxrtlWorker { if (!design->selected_whole_module(module)) if (design->selected_module(module)) - log_cmd_error("Can't handle partially selected module `%s'!\n", id2cstr(module->name)); + log_cmd_error("Can't handle partially selected module `%s'!\n", module); if (!design->selected_module(module)) continue; diff --git a/docs/source/code_examples/stubnets/stubnets.cc b/docs/source/code_examples/stubnets/stubnets.cc index 566d24b18..41fb66e82 100644 --- a/docs/source/code_examples/stubnets/stubnets.cc +++ b/docs/source/code_examples/stubnets/stubnets.cc @@ -27,7 +27,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // count output lines for this module (needed only for summary output at the end) int line_count = 0; - log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name)); + log("Looking for stub wires in module %s:\n", module); // For all ports on all cells for (auto &cell_iter : module->cells_) @@ -74,11 +74,11 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // report stub bits and/or stub wires, don't report single bits // if called with report_bits set to false. if (GetSize(stub_bits) == GetSize(sig)) { - log(" found stub wire: %s\n", RTLIL::id2cstr(wire->name)); + log(" found stub wire: %s\n", wire); } else { if (!report_bits) continue; - log(" found wire with stub bits: %s [", RTLIL::id2cstr(wire->name)); + log(" found wire with stub bits: %s [", wire); for (int bit : stub_bits) log("%s%d", bit == *stub_bits.begin() ? "" : ", ", bit); log("]\n"); diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index ec3d21ccd..6b876c0f1 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1492,10 +1492,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma design->add(module); if (is_blackbox(nl)) { - log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name)); + log("Importing blackbox module %s.\n", module); module->set_bool_attribute(ID::blackbox); } else { - log("Importing module %s.\n", RTLIL::id2cstr(module->name)); + log("Importing module %s.\n", module); } import_attributes(module->attributes, nl, nl); if (module->name.isPublic()) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 020a4ec0c..31efff63d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1579,7 +1579,7 @@ void RTLIL::Module::makeblackbox() void RTLIL::Module::expand_interfaces(RTLIL::Design *, const dict &) { - log_error("Class doesn't support expand_interfaces (module: `%s')!\n", id2cstr(name)); + log_error("Class doesn't support expand_interfaces (module: `%s')!\n", name.unescape()); } bool RTLIL::Module::reprocess_if_necessary(RTLIL::Design *) @@ -1591,7 +1591,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dictname)); + log(" %s", c); cell2scc[c] = sccList.size(); scc.insert(c); } @@ -201,7 +201,7 @@ struct SccWorker if (!nofeedbackMode && cellToNextCell[cell].count(cell)) { log("Found an SCC:"); pool scc; - log(" %s", RTLIL::id2cstr(cell->name)); + log(" %s", cell); cell2scc[cell] = sccList.size(); scc.insert(cell); sccList.push_back(scc); @@ -221,7 +221,7 @@ struct SccWorker run(cell, 0, maxDepth); } - log("Found %d SCCs in module %s.\n", int(sccList.size()), RTLIL::id2cstr(module->name)); + log("Found %d SCCs in module %s.\n", int(sccList.size()), module); } void select(RTLIL::Selection &sel) diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index bcb34d1d4..1fcc35dfa 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -25,8 +25,6 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -using RTLIL::id2cstr; - static std::vector work_stack; static bool match_ids(RTLIL::IdString id, const std::string &pattern) @@ -1022,9 +1020,9 @@ static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::S for (auto mod : design->all_selected_modules()) { if (whole_modules && sel->selected_whole_module(mod->name)) - desc += stringf("%s\n", id2cstr(mod->name)); + desc += stringf("%s\n", mod); for (auto it : mod->selected_members()) - desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(it->name)); + desc += stringf("%s/%s\n", mod, it); } if (push_selection) design->pop_selection(); return desc; @@ -1414,7 +1412,7 @@ struct SelectPass : public Pass { if (arg == "-module" && argidx+1 < args.size()) { RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]); if (design->module(mod_name) == nullptr) - log_cmd_error("No such module: %s\n", id2cstr(mod_name)); + log_cmd_error("No such module: %s\n", mod_name.unescape()); design->selected_active_module = mod_name.str(); got_module = true; continue; @@ -1527,10 +1525,10 @@ struct SelectPass : public Pass { for (auto mod : design->all_selected_modules()) { if (sel->selected_whole_module(mod->name) && list_mode) - log("%s\n", id2cstr(mod->name)); + log("%s\n", mod); if (!list_mod_mode) for (auto it : mod->selected_members()) - LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(it->name)) + LOG_OBJECT("%s/%s\n", mod->name.unescape().c_str(), it->name.unescape().c_str()) } if (count_mode) { @@ -1654,10 +1652,10 @@ struct SelectPass : public Pass { if (sel.full_selection) log("*\n"); for (auto &it : sel.selected_modules) - log("%s\n", id2cstr(it)); + log("%s\n", it.unescape()); for (auto &it : sel.selected_members) for (auto &it2 : it.second) - log("%s/%s\n", id2cstr(it.first), id2cstr(it2)); + log("%s/%s\n", it.first.unescape(), it2.unescape()); return; } @@ -1779,7 +1777,7 @@ static void log_matches(const char *title, Module *module, const T &list) log("\n%d %s:\n", int(matches.size()), title); std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str()); for (auto id : matches) - log(" %s\n", RTLIL::id2cstr(id)); + log(" %s\n", id.unescape()); } } diff --git a/passes/cmds/test_select.cc b/passes/cmds/test_select.cc index 0076500ce..4a3bbc539 100644 --- a/passes/cmds/test_select.cc +++ b/passes/cmds/test_select.cc @@ -144,10 +144,10 @@ struct TestSelectPass : public Pass { for (auto *mod : sub_sel) { if (mod->is_selected_whole()) { - log_debug(" Adding %s.\n", id2cstr(mod->name)); + log_debug(" Adding %s.\n", mod); selected_modules.insert(mod->name); } else for (auto *memb : mod->selected_members()) { - log_debug(" Adding %s.%s.\n", id2cstr(mod->name), id2cstr(memb->name)); + log_debug(" Adding %s.%s.\n", mod, memb); selected_members[mod->name].insert(memb); } } diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index 3aa3fac63..602ad776d 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -285,11 +285,11 @@ struct EquivMakeWorker for (int i = 0; i < wire->width; i++) { if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) { - log(" Skipping signal bit %s [%d]: undriven on gold side.\n", id2cstr(gold_wire->name), i); + log(" Skipping signal bit %s [%d]: undriven on gold side.\n", gold_wire, i); continue; } if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) { - log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i); + log(" Skipping signal bit %s [%d]: undriven on gate side.\n", gate_wire, i); continue; } equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index dfe99f512..7f5107ce9 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -61,7 +61,7 @@ ret_false: if (recursion_monitor.count(cellport.first)) { log_warning("logic loop in mux tree at signal %s in module %s.\n", - log_signal(sig), RTLIL::id2cstr(module->name)); + log_signal(sig), module); goto ret_false; } diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 67475eda0..f41c19672 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -87,7 +87,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, if (decl.index > 0) { portwidths[decl.portname] = max(portwidths[decl.portname], 1); portwidths[decl.portname] = max(portwidths[decl.portname], portwidths[stringf("$%d", decl.index)]); - log(" port %d: %s [%d:0] %s\n", decl.index, decl.input ? decl.output ? "inout" : "input" : "output", portwidths[decl.portname]-1, RTLIL::id2cstr(decl.portname)); + log(" port %d: %s [%d:0] %s\n", decl.index, decl.input ? decl.output ? "inout" : "input" : "output", portwidths[decl.portname]-1, RTLIL::unescape_id(decl.portname)); if (indices.count(decl.index) > ports.size()) log_error("Port index (%d) exceeds number of found ports (%d).\n", decl.index, int(ports.size())); if (indices.count(decl.index) == 0) @@ -108,10 +108,10 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, indices.erase(d.index); ports[d.index-1] = d; portwidths[d.portname] = max(portwidths[d.portname], 1); - log(" port %d: %s [%d:0] %s\n", d.index, d.input ? d.output ? "inout" : "input" : "output", portwidths[d.portname]-1, RTLIL::id2cstr(d.portname)); + log(" port %d: %s [%d:0] %s\n", d.index, d.input ? d.output ? "inout" : "input" : "output", portwidths[d.portname]-1, RTLIL::unescape_id(d.portname)); goto found_matching_decl; } - log_error("Can't match port %s.\n", RTLIL::id2cstr(portname)); + log_error("Can't match port %s.\n", portname.unescape()); found_matching_decl:; portnames.erase(portname); } @@ -133,9 +133,9 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, mod->fixup_ports(); for (auto ¶ : parameters) - log(" ignoring parameter %s.\n", RTLIL::id2cstr(para)); + log(" ignoring parameter %s.\n", para.unescape()); - log(" module %s created.\n", RTLIL::id2cstr(mod->name)); + log(" module %s created.\n", mod); } } @@ -597,7 +597,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check int idx = it.second.first, num = it.second.second; if (design->module(cell->type) == nullptr) - log_error("Array cell `%s.%s' of unknown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + log_error("Array cell `%s.%s' of unknown type `%s'.\n", module, cell, cell->type.unescape()); RTLIL::Module *mod = design->module(cell->type); @@ -613,12 +613,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check } } if (mod->wire(portname) == nullptr) - log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); + log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", module, cell, conn.first.unescape()); int port_size = mod->wire(portname)->width; if (conn_size == port_size || conn_size == 0) continue; if (conn_size != port_size*num) - log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); + log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", module, cell, conn.first.unescape()); conn.second = conn.second.extract(port_size*idx, port_size); } } @@ -1219,7 +1219,7 @@ struct HierarchyPass : public Pass { if (read_id_num(p.first, &id)) { if (id <= 0 || id > GetSize(cell_mod->avail_parameters)) { log(" Failed to map positional parameter %d of cell %s.%s (%s).\n", - id, RTLIL::id2cstr(mod->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + id, mod, cell, cell->type.unescape()); } else { params_rename.insert(std::make_pair(p.first, cell_mod->avail_parameters[id - 1])); } @@ -1241,7 +1241,7 @@ struct HierarchyPass : public Pass { RTLIL::Module *module = work.first; RTLIL::Cell *cell = work.second; log("Mapping positional arguments of cell %s.%s (%s).\n", - RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + module, cell, cell->type.unescape()); dict new_connections; for (auto &conn : cell->connections()) { int id; @@ -1249,7 +1249,7 @@ struct HierarchyPass : public Pass { std::pair key(design->module(cell->type), id); if (pos_map.count(key) == 0) { log(" Failed to map positional argument %d of cell %s.%s (%s).\n", - id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + id, module, cell, cell->type.unescape()); new_connections[conn.first] = conn.second; } else new_connections[pos_map.at(key)] = conn.second; @@ -1283,7 +1283,7 @@ struct HierarchyPass : public Pass { if (m == nullptr) log_error("Cell %s.%s (%s) has implicit port connections but the module it instantiates is unknown.\n", - RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + module, cell, cell->type.unescape()); // Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) { @@ -1312,11 +1312,11 @@ struct HierarchyPass : public Pass { if (parent_wire == nullptr) log_error("No matching wire for implicit port connection `%s' of cell %s.%s (%s).\n", - RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + wire, module, cell, cell->type.unescape()); if (parent_wire->width != wire->width) log_error("Width mismatch between wire (%d bits) and port (%d bits) for implicit port connection `%s' of cell %s.%s (%s).\n", parent_wire->width, wire->width, - RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + wire, module, cell, cell->type.unescape()); cell->setPort(wire->name, parent_wire); } cell->attributes.erase(ID::wildcard_port_conns); diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index ff1ae2628..6c4023a6a 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -132,7 +132,7 @@ struct CutpointPass : public Pass { if (cell->input(conn.first)) for (auto bit : sigmap(conn.second)) if (wire_drivers.count(bit)) { - log_debug(" Treating inout port '%s' as input.\n", id2cstr(conn.first)); + log_debug(" Treating inout port '%s' as input.\n", conn.first.unescape()); do_cut = false; break; } @@ -140,7 +140,7 @@ struct CutpointPass : public Pass { if (do_cut) { module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second))); if (cell->input(conn.first)) { - log_debug(" Treating inout port '%s' as output.\n", id2cstr(conn.first)); + log_debug(" Treating inout port '%s' as output.\n", conn.first.unescape()); for (auto bit : sigmap(conn.second)) wire_drivers.insert(bit); } diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index ef00a6956..b5f2a437c 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -471,7 +471,7 @@ struct ExposePass : public Pass { { if (!w->port_input) { w->port_input = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name)); + log("New module port: %s/%s\n", module, w); wire_map[w] = NEW_ID; } } @@ -479,7 +479,7 @@ struct ExposePass : public Pass { { if (!w->port_output) { w->port_output = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name)); + log("New module port: %s/%s\n", module, w); } if (flag_cut) { @@ -555,7 +555,7 @@ struct ExposePass : public Pass { RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width); wire_q->port_input = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_q->name)); + log("New module port: %s/%s\n", module, wire_q); RTLIL::SigSig connect_q; for (size_t i = 0; i < wire_bits_vec.size(); i++) { @@ -569,12 +569,12 @@ struct ExposePass : public Pass { RTLIL::Wire *wire_d = add_new_wire(module, wire->name.str() + sep + "d", wire->width); wire_d->port_output = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name)); + log("New module port: %s/%s\n", module, wire_d); module->connect(RTLIL::SigSig(wire_d, info.sig_d)); RTLIL::Wire *wire_c = add_new_wire(module, wire->name.str() + sep + "c"); wire_c->port_output = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name)); + log("New module port: %s/%s\n", module, wire_c); if (info.clk_polarity) { module->connect(RTLIL::SigSig(wire_c, info.sig_clk)); } else { @@ -590,7 +590,7 @@ struct ExposePass : public Pass { { RTLIL::Wire *wire_r = add_new_wire(module, wire->name.str() + sep + "r"); wire_r->port_output = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name)); + log("New module port: %s/%s\n", module, wire_r); if (info.arst_polarity) { module->connect(RTLIL::SigSig(wire_r, info.sig_arst)); } else { @@ -604,7 +604,7 @@ struct ExposePass : public Pass { RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width); wire_v->port_output = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name)); + log("New module port: %s/%s\n", module, wire_v); module->connect(RTLIL::SigSig(wire_v, info.arst_value)); } } @@ -638,7 +638,7 @@ struct ExposePass : public Pass { if (p->port_output) w->port_input = true; - log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); + log("New module port: %s/%s (%s)\n", module, w, cell->type.unescape()); RTLIL::SigSpec sig; if (cell->hasPort(p->name)) @@ -660,7 +660,7 @@ struct ExposePass : public Pass { if (ct.cell_output(cell->type, it.first)) w->port_input = true; - log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); + log("New module port: %s/%s (%s)\n", module, w, cell->type.unescape()); if (w->port_input) module->connect(RTLIL::SigSig(it.second, w)); diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 4b0669c25..d2ca52b6f 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -139,7 +139,7 @@ struct FindReducedInputs if (ez_cells.count(drv.first) == 0) { satgen.setContext(&sigmap, "A"); if (!satgen.importCell(drv.first)) - log_error("Can't create SAT model for cell %s (%s)!\n", RTLIL::id2cstr(drv.first->name), RTLIL::id2cstr(drv.first->type)); + log_error("Can't create SAT model for cell %s (%s)!\n", drv.first, drv.first->type.unescape()); satgen.setContext(&sigmap, "B"); if (!satgen.importCell(drv.first)) log_abort(); @@ -256,7 +256,7 @@ struct PerformReduction std::pair> &drv = drivers.at(out); if (celldone.count(drv.first) == 0) { if (!satgen.importCell(drv.first)) - log_error("Can't create SAT model for cell %s (%s)!\n", RTLIL::id2cstr(drv.first->name), RTLIL::id2cstr(drv.first->type)); + log_error("Can't create SAT model for cell %s (%s)!\n", drv.first, drv.first->type.unescape()); celldone.insert(drv.first); } int max_child_depth = 0; @@ -595,14 +595,14 @@ struct FreduceWorker void dump() { - std::string filename = stringf("%s_%s_%05d.il", dump_prefix, RTLIL::id2cstr(module->name), reduce_counter); + std::string filename = stringf("%s_%s_%05d.il", dump_prefix, module, reduce_counter); log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename); Pass::call(design, stringf("dump -outfile %s %s", filename, design->selected_active_module.empty() ? module->name.c_str() : "")); } int run() { - log("Running functional reduction on module %s:\n", RTLIL::id2cstr(module->name)); + log("Running functional reduction on module %s:\n", module); CellTypes ct; ct.setup_internals(); @@ -749,7 +749,7 @@ struct FreduceWorker } } - log(" Rewired a total of %d signal bits in module %s.\n", rewired_sigbits, RTLIL::id2cstr(module->name)); + log(" Rewired a total of %d signal bits in module %s.\n", rewired_sigbits, module); return rewired_sigbits; } }; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 55a41909d..9df88b304 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -128,7 +128,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name); } - log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name)); + log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", miter_name.unescape(), gold_name.unescape(), gate_name.unescape()); RTLIL::Module *miter_module = new RTLIL::Module; miter_module->name = miter_name; diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index d7667d6f5..0a12d4881 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -389,7 +389,7 @@ struct IopadmapPass : public Pass { if (wire->port_input && !wire->port_output) { if (inpad_celltype.empty()) { - log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); + log("Don't map input port %s.%s: Missing option -inpad.\n", module, wire); continue; } celltype = inpad_celltype; @@ -398,7 +398,7 @@ struct IopadmapPass : public Pass { } else if (!wire->port_input && wire->port_output) { if (outpad_celltype.empty()) { - log("Don't map output port %s.%s: Missing option -outpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); + log("Don't map output port %s.%s: Missing option -outpad.\n", module, wire); continue; } celltype = outpad_celltype; @@ -407,7 +407,7 @@ struct IopadmapPass : public Pass { } else if (wire->port_input && wire->port_output) { if (inoutpad_celltype.empty()) { - log("Don't map inout port %s.%s: Missing option -inoutpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); + log("Don't map inout port %s.%s: Missing option -inoutpad.\n", module, wire); continue; } celltype = inoutpad_celltype; @@ -417,11 +417,11 @@ struct IopadmapPass : public Pass { log_abort(); if (!flag_bits && wire->width != 1 && widthparam.empty()) { - log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); + log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", module, wire); continue; } - log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype); + log("Mapping port %s.%s using %s.\n", module, wire, celltype); if (flag_bits) { @@ -442,7 +442,7 @@ struct IopadmapPass : public Pass { if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); if (!nameparam.empty()) - cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i)); + cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", wire, i)); cell->attributes[ID::keep] = RTLIL::Const(1); } } @@ -465,7 +465,7 @@ struct IopadmapPass : public Pass { if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); if (!nameparam.empty()) - cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name)); + cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(wire->name.unescape()); cell->attributes[ID::keep] = RTLIL::Const(1); } diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc index 0d07e2522..4a1849642 100644 --- a/techlibs/ice40/ice40_braminit.cc +++ b/techlibs/ice40/ice40_braminit.cc @@ -46,7 +46,7 @@ static void run_ice40_braminit(Module *module) continue; /* Open file */ - log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file); + log("Processing %s : %s\n", cell, init_file); std::ifstream f; f.open(init_file.c_str()); From 75dcbe03c6a61beb893967766fa8e2bac095446a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 15 May 2026 15:54:07 +0200 Subject: [PATCH 07/30] Convert RTLIL::unescape_id of IdString to unescape() --- backends/aiger2/aiger.cc | 10 +- backends/blif/blif.cc | 4 +- backends/edif/edif.cc | 20 +- backends/functional/cxx.cc | 2 +- backends/functional/smtlib.cc | 4 +- backends/functional/smtlib_rosette.cc | 6 +- backends/functional/test_generic.cc | 6 +- backends/intersynth/intersynth.cc | 2 +- backends/jny/jny.cc | 14 +- backends/json/json.cc | 2 +- backends/spice/spice.cc | 2 +- frontends/liberty/liberty.cc | 24 +- kernel/functional.cc | 8 +- kernel/functional.h | 2 +- kernel/log.cc | 2 +- kernel/satgen.h | 2 +- kernel/scopeinfo.cc | 4 +- kernel/yosys.cc | 10 +- passes/cmds/icell_liberty.cc | 6 +- passes/cmds/portarcs.cc | 2 +- passes/cmds/rename.cc | 2 +- passes/cmds/show.cc | 2 +- passes/cmds/wrapcell.cc | 2 +- passes/equiv/equiv_make.cc.orig | 520 ++++++++++++++++++++++++++ passes/fsm/fsm_recode.cc | 4 +- passes/hierarchy/flatten.cc | 6 +- passes/hierarchy/hierarchy.cc | 6 +- passes/sat/cutpoint.cc | 2 +- passes/sat/expose.cc | 4 +- passes/sat/miter.cc | 12 +- passes/sat/sim.cc | 40 +- passes/techmap/abc.cc | 4 +- passes/techmap/extract.cc | 8 +- passes/techmap/techmap.cc | 4 +- techlibs/common/opensta.cc | 2 +- 35 files changed, 636 insertions(+), 114 deletions(-) create mode 100644 passes/equiv/equiv_make.cc.orig diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 6d8ac8a24..0dceaedd6 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -560,9 +560,9 @@ struct Index { if (!first) ret += "."; if (!cell) - ret += RTLIL::unescape_id(minfo.module->name); + ret += minfo.module->name.unescape(); else - ret += RTLIL::unescape_id(cell->name); + ret += cell->name.unescape(); first = false; } return ret; @@ -844,7 +844,7 @@ struct AigerWriter : Index { char buf[32]; snprintf(buf, sizeof(buf), "o%d ", i); f->write(buf, strlen(buf)); - std::string name = RTLIL::unescape_id(bit.wire->name); + std::string name = bit.wire->name.unescape(); f->write(name.data(), name.size()); f->put('\n'); } @@ -857,7 +857,7 @@ struct AigerWriter : Index { char buf[32]; snprintf(buf, sizeof(buf), "i%d ", i); f->write(buf, strlen(buf)); - std::string name = RTLIL::unescape_id(bit.wire->name); + std::string name = bit.wire->name.unescape(); f->write(name.data(), name.size()); f->put('\n'); } @@ -1088,7 +1088,7 @@ struct XAigerWriter : AigerWriter { for (auto box : minfo.found_blackboxes) { log_debug(" - %s.%s (type %s): ", cursor.path(), - RTLIL::unescape_id(box->name), + box, box->type.unescape()); Module *box_module = design->module(box->type), *box_derived; diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index d16d39e5e..ac2e4edde 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -91,7 +91,7 @@ struct BlifDumper const std::string str(RTLIL::IdString id) { - std::string str = RTLIL::unescape_id(id); + std::string str = id.unescape(); for (size_t i = 0; i < str.size(); i++) if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>') str[i] = '?'; @@ -108,7 +108,7 @@ struct BlifDumper return config->undef_type == "-" || config->undef_type == "+" ? config->undef_out.c_str() : "$undef"; } - std::string str = RTLIL::unescape_id(sig.wire->name); + std::string str = sig.wire->name.unescape(); for (size_t i = 0; i < str.size(); i++) if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>') str[i] = '?'; diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 180c3739b..9d3392e99 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -30,9 +30,11 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -#define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true) -#define EDIF_DEFR(_id, _ren, _bl, _br) edif_names(RTLIL::unescape_id(_id), true, _ren, _bl, _br) -#define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false) +#define EDIF_DEF(_id) edif_names(_id.unescape(), true) +#define EDIF_DEFR(_id, _ren, _bl, _br) edif_names(_id.unescape(), true, _ren, _bl, _br) +#define EDIF_REF(_id) edif_names(_id.unescape(), false) +#define EDIF_DEF_STR(_id) edif_names(RTLIL::unescape_id(_id), true) +#define EDIF_REF_STR(_id) edif_names(RTLIL::unescape_id(_id), false) struct EdifNames { @@ -227,7 +229,7 @@ struct EdifBackend : public Backend { if (top_module_name.empty()) log_error("No module found in design!\n"); - *f << stringf("(edif %s\n", EDIF_DEF(top_module_name)); + *f << stringf("(edif %s\n", EDIF_DEF_STR(top_module_name)); *f << stringf(" (edifVersion 2 0 0)\n"); *f << stringf(" (edifLevel 0)\n"); *f << stringf(" (keywordMap (keywordLevel 0))\n"); @@ -534,7 +536,7 @@ struct EdifBackend : public Backend { if (netname[i] == ' ' || netname[i] == '\\') netname.erase(netname.begin() + i--); } - *f << stringf(" (net %s (joined\n", EDIF_DEF(netname)); + *f << stringf(" (net %s (joined\n", EDIF_DEF_STR(netname)); for (auto &ref : it.second) *f << stringf(" %s\n", ref.first); if (sig.wire == NULL) { @@ -572,7 +574,7 @@ struct EdifBackend : public Backend { if (keepmode) { - *f << stringf(" (net %s (joined\n", EDIF_DEF(netname)); + *f << stringf(" (net %s (joined\n", EDIF_DEF_STR(netname)); auto &refs = net_join_db.at(mapped_sig); for (auto &ref : refs) @@ -588,7 +590,7 @@ struct EdifBackend : public Backend { } else { - log_warning("Ignoring conflicting 'keep' property on net %s. Use -keep to generate the extra net nevertheless.\n", EDIF_DEF(netname)); + log_warning("Ignoring conflicting 'keep' property on net %s. Use -keep to generate the extra net nevertheless.\n", EDIF_DEF_STR(netname)); } } } @@ -599,8 +601,8 @@ struct EdifBackend : public Backend { } *f << stringf(" )\n"); - *f << stringf(" (design %s\n", EDIF_DEF(top_module_name)); - *f << stringf(" (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name)); + *f << stringf(" (design %s\n", EDIF_DEF_STR(top_module_name)); + *f << stringf(" (cellRef %s (libraryRef DESIGN))\n", EDIF_REF_STR(top_module_name)); *f << stringf(" )\n"); *f << stringf(")\n"); diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 7f4ad1ea7..d67bc9143 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -89,7 +89,7 @@ struct CxxStruct { } f.print("\n\t\ttemplate void visit(T &&fn) {{\n"); for (auto p : types) { - f.print("\t\t\tfn(\"{}\", {});\n", RTLIL::unescape_id(p.first), scope(p.first, p.first)); + f.print("\t\t\tfn(\"{}\", {});\n", p.first.unescape(), scope(p.first, p.first)); } f.print("\t\t}}\n"); f.print("\t}};\n\n"); diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 1504c8fba..0451af4c7 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -80,7 +80,7 @@ public: SmtStruct(std::string name, SmtScope &scope) : scope(scope), name(name) {} void insert(IdString field_name, SmtSort sort) { field_names(field_name); - auto accessor = scope.unique_name("\\" + name + "_" + RTLIL::unescape_id(field_name)); + auto accessor = scope.unique_name("\\" + name + "_" + field_name.unescape()); fields.emplace_back(Field{sort, accessor}); } void write_definition(SExprWriter &w) { @@ -99,7 +99,7 @@ public: w.open(list(name)); for(auto field_name : field_names) { w << fn(field_name); - w.comment(RTLIL::unescape_id(field_name), true); + w.comment(field_name.unescape(), true); } w.close(); } diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc index 73e1b48c6..b37f948b6 100644 --- a/backends/functional/smtlib_rosette.cc +++ b/backends/functional/smtlib_rosette.cc @@ -106,7 +106,7 @@ public: w.open(list(name)); for(auto field_name : field_names) { w << fn(field_name); - w.comment(RTLIL::unescape_id(field_name), true); + w.comment(field_name.unescape(), true); } w.close(); } @@ -281,7 +281,7 @@ struct SmtrModule { w.push(); w.open(list()); w.open(list("assoc-result")); - w << list("assoc", "\"" + RTLIL::unescape_id(input->name) + "\"", inputs_name); + w << list("assoc", "\"" + input->name.unescape() + "\"", inputs_name); w.pop(); w.open(list("if", "assoc-result")); w << list("cdr", "assoc-result"); @@ -298,7 +298,7 @@ struct SmtrModule { w << list(*output_helper_name, outputs_name); w.open(list("list")); for (auto output : ir.outputs()) { - w << list("cons", "\"" + RTLIL::unescape_id(output->name) + "\"", output_struct.access("outputs", output->name)); + w << list("cons", "\"" + output->name.unescape() + "\"", output_struct.access("outputs", output->name)); } w.pop(); } diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc index c01649a0f..343fcfc0f 100644 --- a/backends/functional/test_generic.cc +++ b/backends/functional/test_generic.cc @@ -146,11 +146,11 @@ struct FunctionalTestGeneric : public Pass log("Dumping module `%s'.\n", module->name); auto fir = Functional::IR::from_module(module); for(auto node : fir) - std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n"; + std::cout << node.name().unescape() << " = " << node.to_string([](auto n) { return n.name().unescape(); }) << "\n"; for(auto output : fir.all_outputs()) - std::cout << RTLIL::unescape_id(output->kind) << " " << RTLIL::unescape_id(output->name) << " = " << RTLIL::unescape_id(output->value().name()) << "\n"; + std::cout << output->kind.unescape() << " " << output->name.unescape() << " = " << output->value().name().unescape() << "\n"; for(auto state : fir.all_states()) - std::cout << RTLIL::unescape_id(state->kind) << " " << RTLIL::unescape_id(state->name) << " = " << RTLIL::unescape_id(state->next_value().name()) << "\n"; + std::cout << state->kind.unescape() << " " << state->name.unescape() << " = " << state->next_value().name().unescape() << "\n"; } } } FunctionalCxxBackend; diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 5e1a3fc8d..1704ba429 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -41,7 +41,7 @@ static std::string netname(std::set &conntypes_code, std::setname); + return sig.as_wire()->name.unescape(); } struct IntersynthBackend : public Backend { diff --git a/backends/jny/jny.cc b/backends/jny/jny.cc index ee0c0d14c..00650f5d8 100644 --- a/backends/jny/jny.cc +++ b/backends/jny/jny.cc @@ -91,7 +91,7 @@ struct JnyWriter { _cells.clear(); for (auto cell : mod->cells()) { - const auto cell_type = escape_string(RTLIL::unescape_id(cell->type)); + const auto cell_type = escape_string(cell->type.unescape()); if (_cells.find(cell_type) == _cells.end()) _cells.emplace(cell_type, std::vector()); @@ -214,7 +214,7 @@ struct JnyWriter void write_cell_conn(const std::pair& sig, uint16_t indent_level = 0) { const auto _indent = gen_indent(indent_level); f << _indent << " {\n"; - f << _indent << " \"name\": \"" << escape_string(RTLIL::unescape_id(sig.first)) << "\",\n"; + f << _indent << " \"name\": \"" << escape_string(sig.first.unescape()) << "\",\n"; f << _indent << " \"signals\": [\n"; write_sigspec(sig.second, indent_level + 2); @@ -232,7 +232,7 @@ struct JnyWriter const auto _indent = gen_indent(indent_level); f << _indent << "{\n"; - f << stringf(" %s\"name\": \"%s\",\n", _indent, escape_string(RTLIL::unescape_id(mod->name))); + f << stringf(" %s\"name\": \"%s\",\n", _indent, escape_string(mod->name.unescape())); f << _indent << " \"cell_sorts\": [\n"; bool first_sort{true}; @@ -280,7 +280,7 @@ struct JnyWriter f << ",\n"; f << _indent << " {\n"; - f << stringf(" %s\"name\": \"%s\",\n", _indent, escape_string(RTLIL::unescape_id(con.first))); + f << stringf(" %s\"name\": \"%s\",\n", _indent, escape_string(con.first.unescape())); f << _indent << " \"direction\": \""; if (port_cell->input(con.first)) f << "i"; @@ -351,10 +351,10 @@ struct JnyWriter f << stringf(",\n"); const auto param_val = param.second; if (!param_val.empty()) { - f << stringf(" %s\"%s\": ", _indent, escape_string(RTLIL::unescape_id(param.first))); + f << stringf(" %s\"%s\": ", _indent, escape_string(param.first.unescape())); write_param_val(param_val); } else { - f << stringf(" %s\"%s\": true", _indent, escape_string(RTLIL::unescape_id(param.first))); + f << stringf(" %s\"%s\": true", _indent, escape_string(param.first.unescape())); } first_param = false; @@ -366,7 +366,7 @@ struct JnyWriter log_assert(cell != nullptr); f << _indent << " {\n"; - f << stringf(" %s\"name\": \"%s\"", _indent, escape_string(RTLIL::unescape_id(cell->name))); + f << stringf(" %s\"name\": \"%s\"", _indent, escape_string(cell->name.unescape())); if (_include_connections) { f << ",\n" << _indent << " \"connections\": [\n"; diff --git a/backends/json/json.cc b/backends/json/json.cc index 234574ed1..23d18fb15 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -76,7 +76,7 @@ struct JsonWriter string get_name(IdString name) { - return get_string(RTLIL::unescape_id(name)); + return get_string(name.unescape()); } string get_bits(SigSpec sig) diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 36caf6359..5f14a2a66 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -30,7 +30,7 @@ PRIVATE_NAMESPACE_BEGIN static string spice_id2str(IdString id) { static const char *escape_chars = "$\\[]()<>="; - string s = RTLIL::unescape_id(id); + string s = id.unescape(); for (auto &ch : s) if (strchr(escape_chars, ch) != nullptr) ch = '_'; diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index a006ae649..447f438a8 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -41,14 +41,14 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *& expr[id_len] == '_' || expr[id_len] == '[' || expr[id_len] == ']') id_len++; if (id_len == 0) - log_error("Expected identifier at `%s' in %s.\n", expr, RTLIL::unescape_id(module->name)); + log_error("Expected identifier at `%s' in %s.\n", expr, module); if (id_len == 1 && (*expr == '0' || *expr == '1')) return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1; std::string id = RTLIL::escape_id(std::string(expr, id_len)); if (!module->wires_.count(id)) - log_error("Can't resolve wire name %s in %s.\n", RTLIL::unescape_id(id), RTLIL::unescape_id(module->name)); + log_error("Can't resolve wire name %s in %s.\n", RTLIL::unescape_id(id), module); expr += id_len; return module->wires_.at(id); @@ -175,7 +175,7 @@ static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr) #endif if (stack.size() != 1 || stack.back().type != 3) - log_error("Parser error in function expr `%s'in %s.\n", orig_expr, RTLIL::unescape_id(module->name)); + log_error("Parser error in function expr `%s'in %s.\n", orig_expr, module); return stack.back().sig; } @@ -211,7 +211,7 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node) auto [iq_sig, iqn_sig] = find_latch_ff_wires(module, node); RTLIL::SigSpec clk_sig, data_sig, clear_sig, preset_sig; bool clk_polarity = true, clear_polarity = true, preset_polarity = true; - const std::string name = RTLIL::unescape_id(module->name); + const std::string name = module->name.unescape(); std::optional clear_preset_var1; std::optional clear_preset_var2; @@ -339,9 +339,9 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla if (enable_sig.size() == 0 || data_sig.size() == 0) { if (!flag_ignore_miss_data_latch) - log_error("Latch cell %s has no data_in and/or enable attribute.\n", RTLIL::unescape_id(module->name)); + log_error("Latch cell %s has no data_in and/or enable attribute.\n", module); else - log("Ignored latch cell %s with no data_in and/or enable attribute.\n", RTLIL::unescape_id(module->name)); + log("Ignored latch cell %s with no data_in and/or enable attribute.\n", module); return false; } @@ -632,9 +632,9 @@ struct LibertyFrontend : public Frontend { { if (!flag_ignore_miss_dir) { - log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0), RTLIL::unescape_id(module->name)); + log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0), module); } else { - log("Ignoring cell %s with missing or invalid direction for pin %s.\n", RTLIL::unescape_id(module->name), node->args.at(0)); + log("Ignoring cell %s with missing or invalid direction for pin %s.\n", module, node->args.at(0)); delete module; goto skip_cell; } @@ -646,7 +646,7 @@ struct LibertyFrontend : public Frontend { if (node->id == "bus" && node->args.size() == 1) { if (flag_ignore_buses) { - log("Ignoring cell %s with a bus interface %s.\n", RTLIL::unescape_id(module->name), node->args.at(0)); + log("Ignoring cell %s with a bus interface %s.\n", module, node->args.at(0)); delete module; goto skip_cell; } @@ -663,7 +663,7 @@ struct LibertyFrontend : public Frontend { } if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal")) - log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0), RTLIL::unescape_id(module->name)); + log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0), module); simple_comb_cell = false; @@ -758,9 +758,9 @@ struct LibertyFrontend : public Frontend { if (dir->value != "inout") { // allow inout with missing function, can be used for power pins if (!flag_ignore_miss_func) { - log_error("Missing function on output %s of cell %s.\n", RTLIL::unescape_id(wire->name), RTLIL::unescape_id(module->name)); + log_error("Missing function on output %s of cell %s.\n", wire, module); } else { - log("Ignoring cell %s with missing function on output %s.\n", RTLIL::unescape_id(module->name), RTLIL::unescape_id(wire->name)); + log("Ignoring cell %s with missing function on output %s.\n", module, wire); delete module; goto skip_cell; } diff --git a/kernel/functional.cc b/kernel/functional.cc index 4d1423b28..d04677332 100644 --- a/kernel/functional.cc +++ b/kernel/functional.cc @@ -136,7 +136,7 @@ struct PrintVisitor : DefaultVisitor { std::string Node::to_string() { - return to_string([](Node n) { return RTLIL::unescape_id(n.name()); }); + return to_string([](Node n) { return n.name().unescape(); }); } std::string Node::to_string(std::function np) @@ -677,7 +677,7 @@ public: factory.update_pending(pending, node); } else { DriveSpec driver = driver_map(DriveSpec(wire_chunk)); - check_undriven(driver, RTLIL::unescape_id(wire_chunk.wire->name)); + check_undriven(driver, wire_chunk.wire->name.unescape()); Node node = enqueue(driver); factory.suggest_name(node, wire_chunk.wire->name); factory.update_pending(pending, node); @@ -695,7 +695,7 @@ public: factory.update_pending(pending, node); } else { DriveSpec driver = driver_map(DriveSpec(port_chunk)); - check_undriven(driver, RTLIL::unescape_id(port_chunk.cell->name) + " port " + RTLIL::unescape_id(port_chunk.port)); + check_undriven(driver, port_chunk.cell->name.unescape() + " port " + port_chunk.port.unescape()); factory.update_pending(pending, enqueue(driver)); } } else { @@ -744,7 +744,7 @@ void IR::topological_sort() { log_warning("Combinational loop:\n"); for (int *i = begin; i != end; ++i) { Node node(_graph[*i]); - log("- %s = %s\n", RTLIL::unescape_id(node.name()), node.to_string()); + log("- %s = %s\n", node.name().unescape(), node.to_string()); } log("\n"); scc = true; diff --git a/kernel/functional.h b/kernel/functional.h index 073adf40a..3334f02c8 100644 --- a/kernel/functional.h +++ b/kernel/functional.h @@ -588,7 +588,7 @@ namespace Functional { _used_names.insert(std::move(name)); } std::string unique_name(IdString suggestion) { - std::string str = RTLIL::unescape_id(suggestion); + std::string str = suggestion.unescape(); for(size_t i = 0; i < str.size(); i++) if(!is_character_legal(str[i], i)) str[i] = substitution_character; diff --git a/kernel/log.cc b/kernel/log.cc index fd3f75502..272b69589 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -614,7 +614,7 @@ std::string log_const(const RTLIL::Const &value, bool autoint) const char *log_id(const RTLIL::IdString &str) { - std::string unescaped = RTLIL::unescape_id(str); + std::string unescaped = str.unescape(); log_id_cache.push_back(strdup(unescaped.c_str())); return log_id_cache.back(); } diff --git a/kernel/satgen.h b/kernel/satgen.h index c11d480a4..722433d62 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -102,7 +102,7 @@ struct SatGen else vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE); } else { - std::string wire_name = RTLIL::unescape_id(bit.wire->name); + std::string wire_name = bit.wire->name.unescape(); std::string name = pf + (bit.wire->width == 1 ? wire_name : stringf("%s [%d]", wire_name, bit.offset)); vec.push_back(ez->frozen_literal(name)); diff --git a/kernel/scopeinfo.cc b/kernel/scopeinfo.cc index 59dd746b5..aac83d564 100644 --- a/kernel/scopeinfo.cc +++ b/kernel/scopeinfo.cc @@ -100,13 +100,13 @@ static const char *attr_prefix(ScopeinfoAttrs attrs) bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, RTLIL::IdString id) { log_assert(scopeinfo->type == ID($scopeinfo)); - return scopeinfo->has_attribute(attr_prefix(attrs) + RTLIL::unescape_id(id)); + return scopeinfo->has_attribute(attr_prefix(attrs) + id.unescape()); } RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, RTLIL::IdString id) { log_assert(scopeinfo->type == ID($scopeinfo)); - auto found = scopeinfo->attributes.find(attr_prefix(attrs) + RTLIL::unescape_id(id)); + auto found = scopeinfo->attributes.find(attr_prefix(attrs) + id.unescape()); if (found == scopeinfo->attributes.end()) return RTLIL::Const(); return found->second; diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 5643ed7b0..de5baaee8 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -953,7 +953,7 @@ static char *readline_obj_generator(const char *text, int state) if (design->selected_active_module.empty()) { for (auto mod : design->modules()) - if (RTLIL::unescape_id(mod->name).compare(0, len, text) == 0) + if (mod->name.unescape().compare(0, len, text) == 0) obj_names.push_back(strdup(mod->name.unescape().c_str())); } else if (design->module(design->selected_active_module) != nullptr) @@ -961,19 +961,19 @@ static char *readline_obj_generator(const char *text, int state) RTLIL::Module *module = design->module(design->selected_active_module); for (auto w : module->wires()) - if (RTLIL::unescape_id(w->name).compare(0, len, text) == 0) + if (w->name.unescape().compare(0, len, text) == 0) obj_names.push_back(strdup(w->name.unescape().c_str())); for (auto &it : module->memories) - if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) + if (it.first.unescape().compare(0, len, text) == 0) obj_names.push_back(strdup(it.first.unescape().c_str())); for (auto cell : module->cells()) - if (RTLIL::unescape_id(cell->name).compare(0, len, text) == 0) + if (cell->name.unescape().compare(0, len, text) == 0) obj_names.push_back(strdup(cell->name.unescape().c_str())); for (auto &it : module->processes) - if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) + if (it.first.unescape().compare(0, len, text) == 0) obj_names.push_back(strdup(it.first.unescape().c_str())); } diff --git a/passes/cmds/icell_liberty.cc b/passes/cmds/icell_liberty.cc index 1d3628f1f..e0a73d08f 100644 --- a/passes/cmds/icell_liberty.cc +++ b/passes/cmds/icell_liberty.cc @@ -71,10 +71,10 @@ struct LibertyStubber { std::sort(sorted_ports.begin(), sorted_ports.end(), cmp); std::string clock_pin_name = ""; for (auto x : sorted_ports) { - std::string port_name = RTLIL::unescape_id(x); + std::string port_name = x.unescape(); bool is_input = base_type.inputs.count(x); bool is_output = base_type.outputs.count(x); - f << "\t\tpin (" << RTLIL::unescape_id(x.str()) << ") {\n"; + f << "\t\tpin (" << x.unescape() << ") {\n"; if (is_input && !is_output) { i.item("direction", "input"); } else if (!is_input && is_output) { @@ -132,7 +132,7 @@ struct LibertyStubber { for (auto x : derived->ports) { bool is_input = base_type.inputs.count(x); bool is_output = base_type.outputs.count(x); - f << "\t\tpin (" << RTLIL::unescape_id(x.str()) << ") {\n"; + f << "\t\tpin (" << x.unescape() << ") {\n"; if (is_input && !is_output) { f << "\t\t\tdirection : input;\n"; } else if (!is_input && is_output) { diff --git a/passes/cmds/portarcs.cc b/passes/cmds/portarcs.cc index 581a8bebf..89a4581ce 100644 --- a/passes/cmds/portarcs.cc +++ b/passes/cmds/portarcs.cc @@ -244,7 +244,7 @@ struct PortarcsPass : Pass { if (draw_mode) { auto bit_str = [](SigBit bit) { - return stringf("%s%d", RTLIL::unescape_id(bit.wire->name.str()), bit.offset); + return stringf("%s%d", bit.wire, bit.offset); }; std::vector headings; diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 2f70126dd..0da132521 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -621,7 +621,7 @@ struct RenamePass : public Pass { RTLIL::Module *module_to_rename = nullptr; for (auto module : design->modules()) - if (module->name == from_name || RTLIL::unescape_id(module->name) == from_name) { + if (module->name == from_name || module->name.unescape() == from_name) { module_to_rename = module; break; } diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index f45a2aeee..919d13b96 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -549,7 +549,7 @@ struct ShowWorker net_conn_map[node].color = nextColor(sig, net_conn_map[node].color); } - std::string proc_src = RTLIL::unescape_id(proc->name); + std::string proc_src = proc->name.unescape(); if (proc->attributes.count(ID::src) > 0) proc_src = proc->attributes.at(ID::src).decode_string(); fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\", %s];\n", pidx, findLabel(proc->name.str()), proc_src.c_str(), findColor(proc->name).c_str()); diff --git a/passes/cmds/wrapcell.cc b/passes/cmds/wrapcell.cc index 1d73decc5..9d73a63c0 100644 --- a/passes/cmds/wrapcell.cc +++ b/passes/cmds/wrapcell.cc @@ -227,7 +227,7 @@ struct WrapcellPass : Pass { if (!unused_outputs.empty()) { context.unused_outputs += "_unused"; for (auto chunk : collect_chunks(unused_outputs)) - context.unused_outputs += "_" + RTLIL::unescape_id(chunk.format(cell)); + context.unused_outputs += "_" + chunk.format(cell).unescape(); } std::optional unescaped_name = format_with_params(name_fmt, cell->parameters, context); diff --git a/passes/equiv/equiv_make.cc.orig b/passes/equiv/equiv_make.cc.orig new file mode 100644 index 000000000..3aa3fac63 --- /dev/null +++ b/passes/equiv/equiv_make.cc.orig @@ -0,0 +1,520 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" +#include "kernel/celltypes.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct EquivMakeWorker +{ + Module *gold_mod, *gate_mod, *equiv_mod; + pool wire_names, cell_names; + CellTypes ct; + + bool inames; + vector blacklists; + vector encfiles; + bool make_assert; + + pool blacklist_names; + dict> encdata; + + pool undriven_bits; + SigMap assign_map; + + void read_blacklists() + { + for (auto fn : blacklists) + { + std::ifstream f(fn); + if (f.fail()) + log_cmd_error("Can't open blacklist file '%s'!\n", fn); + + string line, token; + while (std::getline(f, line)) { + while (1) { + token = next_token(line); + if (token.empty()) + break; + blacklist_names.insert(RTLIL::escape_id(token)); + } + } + } + } + + void read_encfiles() + { + for (auto fn : encfiles) + { + std::ifstream f(fn); + if (f.fail()) + log_cmd_error("Can't open encfile '%s'!\n", fn); + + dict *ed = nullptr; + string line, token; + while (std::getline(f, line)) + { + token = next_token(line); + if (token.empty() || token[0] == '#') + continue; + + if (token == ".fsm") { + IdString modname = RTLIL::escape_id(next_token(line)); + (void)modname; + IdString signame = RTLIL::escape_id(next_token(line)); + if (encdata.count(signame)) + log_cmd_error("Re-definition of signal '%s' in encfile '%s'!\n", signame, fn); + encdata[signame] = dict(); + ed = &encdata[signame]; + continue; + } + + if (token == ".map") { + Const gold_bits = Const::from_string(next_token(line)); + Const gate_bits = Const::from_string(next_token(line)); + (*ed)[gold_bits] = gate_bits; + continue; + } + + log_cmd_error("Syntax error in encfile '%s'!\n", fn); + } + } + } + + void copy_to_equiv() + { + Module *gold_clone = gold_mod->clone(); + Module *gate_clone = gate_mod->clone(); + + for (auto it : gold_clone->wires().to_vector()) { + if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) + wire_names.insert(it->name); + gold_clone->rename(it, it->name.str() + "_gold"); + } + + for (auto it : gold_clone->cells().to_vector()) { + if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) + cell_names.insert(it->name); + gold_clone->rename(it, it->name.str() + "_gold"); + } + + for (auto it : gate_clone->wires().to_vector()) { + if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) + wire_names.insert(it->name); + gate_clone->rename(it, it->name.str() + "_gate"); + } + + for (auto it : gate_clone->cells().to_vector()) { + if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) + cell_names.insert(it->name); + gate_clone->rename(it, it->name.str() + "_gate"); + } + + gold_clone->cloneInto(equiv_mod); + gate_clone->cloneInto(equiv_mod); + delete gold_clone; + delete gate_clone; + } + + void add_eq_assertion(const SigSpec &gold_sig, const SigSpec &gate_sig) + { + auto eq_wire = equiv_mod->Eqx(NEW_ID, gold_sig, gate_sig); + equiv_mod->addAssert(NEW_ID_SUFFIX("assert"), eq_wire, State::S1); + } + + void find_same_wires() + { + SigMap assign_map(equiv_mod); + SigMap rd_signal_map; + SigPool primary_inputs; + + // list of cells without added $equiv cells + auto cells_list = equiv_mod->cells().to_vector(); + + for (auto id : wire_names) + { + IdString gold_id = id.str() + "_gold"; + IdString gate_id = id.str() + "_gate"; + + Wire *gold_wire = equiv_mod->wire(gold_id); + Wire *gate_wire = equiv_mod->wire(gate_id); + + if (encdata.count(id)) + { + log("Creating encoder/decoder for signal %s.\n", id.unescape()); + + Wire *dec_wire = equiv_mod->addWire(id.str() + "_decoded", gold_wire->width); + Wire *enc_wire = equiv_mod->addWire(id.str() + "_encoded", gate_wire->width); + + SigSpec dec_a, dec_b, dec_s; + SigSpec enc_a, enc_b, enc_s; + + dec_a = SigSpec(State::Sx, dec_wire->width); + enc_a = SigSpec(State::Sx, enc_wire->width); + + for (auto &it : encdata.at(id)) + { + SigSpec dec_sig = gate_wire, dec_pat = it.second; + SigSpec enc_sig = dec_wire, enc_pat = it.first; + + if (GetSize(dec_sig) != GetSize(dec_pat)) + log_error("Invalid pattern %s for signal %s of size %d!\n", + log_signal(dec_pat), log_signal(dec_sig), GetSize(dec_sig)); + + if (GetSize(enc_sig) != GetSize(enc_pat)) + log_error("Invalid pattern %s for signal %s of size %d!\n", + log_signal(enc_pat), log_signal(enc_sig), GetSize(enc_sig)); + + SigSpec reduced_dec_sig, reduced_dec_pat; + for (int i = 0; i < GetSize(dec_sig); i++) + if (dec_pat[i] == State::S0 || dec_pat[i] == State::S1) { + reduced_dec_sig.append(dec_sig[i]); + reduced_dec_pat.append(dec_pat[i]); + } + + SigSpec reduced_enc_sig, reduced_enc_pat; + for (int i = 0; i < GetSize(enc_sig); i++) + if (enc_pat[i] == State::S0 || enc_pat[i] == State::S1) { + reduced_enc_sig.append(enc_sig[i]); + reduced_enc_pat.append(enc_pat[i]); + } + + SigSpec dec_result = it.first; + for (auto &bit : dec_result) + if (bit != State::S1) bit = State::S0; + + SigSpec enc_result = it.second; + for (auto &bit : enc_result) + if (bit != State::S1) bit = State::S0; + + SigSpec dec_eq = equiv_mod->addWire(NEW_ID); + SigSpec enc_eq = equiv_mod->addWire(NEW_ID); + + equiv_mod->addEq(NEW_ID, reduced_dec_sig, reduced_dec_pat, dec_eq); + cells_list.push_back(equiv_mod->addEq(NEW_ID, reduced_enc_sig, reduced_enc_pat, enc_eq)); + + dec_s.append(dec_eq); + enc_s.append(enc_eq); + dec_b.append(dec_result); + enc_b.append(enc_result); + } + + equiv_mod->addPmux(NEW_ID, dec_a, dec_b, dec_s, dec_wire); + equiv_mod->addPmux(NEW_ID, enc_a, enc_b, enc_s, enc_wire); + + rd_signal_map.add(assign_map(gate_wire), enc_wire); + gate_wire = dec_wire; + } + + if (gold_wire == nullptr || gate_wire == nullptr || gold_wire->width != gate_wire->width) { + if (gold_wire && gold_wire->port_id) + log_error("Can't match gold port `%s' to a gate port.\n", gold_wire); + if (gate_wire && gate_wire->port_id) + log_error("Can't match gate port `%s' to a gold port.\n", gate_wire); + continue; + } + + log("Presumably equivalent wires: %s (%s), %s (%s) -> %s\n", + gold_wire, log_signal(assign_map(gold_wire)), + gate_wire, log_signal(assign_map(gate_wire)), id.unescape()); + + if (gold_wire->port_output || gate_wire->port_output) + { + gold_wire->port_input = false; + gate_wire->port_input = false; + gold_wire->port_output = false; + gate_wire->port_output = false; + + Wire *wire = equiv_mod->addWire(id, gold_wire->width); + wire->port_output = true; + + if (make_assert) + { + add_eq_assertion(gold_wire, gate_wire); + equiv_mod->connect(wire, gold_wire); + } + else + { + for (int i = 0; i < wire->width; i++) + equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); + } + + rd_signal_map.add(assign_map(gold_wire), wire); + rd_signal_map.add(assign_map(gate_wire), wire); + } + else + if (gold_wire->port_input || gate_wire->port_input) + { + Wire *wire = equiv_mod->addWire(id, gold_wire->width); + wire->port_input = true; + gold_wire->port_input = false; + gate_wire->port_input = false; + equiv_mod->connect(gold_wire, wire); + equiv_mod->connect(gate_wire, wire); + primary_inputs.add(assign_map(gold_wire)); + primary_inputs.add(assign_map(gate_wire)); + primary_inputs.add(wire); + } + else + { + if (make_assert) + add_eq_assertion(gold_wire, gate_wire); + + else { + Wire *wire = equiv_mod->addWire(id, gold_wire->width); + SigSpec rdmap_gold, rdmap_gate, rdmap_equiv; + + for (int i = 0; i < wire->width; i++) { + if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) { + log(" Skipping signal bit %s [%d]: undriven on gold side.\n", id2cstr(gold_wire->name), i); + continue; + } + if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) { + log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i); + continue; + } + equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); + rdmap_gold.append(SigBit(gold_wire, i)); + rdmap_gate.append(SigBit(gate_wire, i)); + rdmap_equiv.append(SigBit(wire, i)); + } + + rd_signal_map.add(rdmap_gold, rdmap_equiv); + rd_signal_map.add(rdmap_gate, rdmap_equiv); + } + } + } + + for (auto c : cells_list) + for (auto &conn : c->connections()) + if (!ct.cell_output(c->type, conn.first)) { + SigSpec old_sig = assign_map(conn.second); + SigSpec new_sig = rd_signal_map(old_sig); + for (int i = 0; i < GetSize(old_sig); i++) + if (primary_inputs.check(old_sig[i])) + new_sig[i] = old_sig[i]; + if (old_sig != new_sig) { + log("Changing input %s of cell %s (%s): %s -> %s\n", + conn.first.unescape(), c, c->type.unescape(), + log_signal(old_sig), log_signal(new_sig)); + c->setPort(conn.first, new_sig); + } + } + + equiv_mod->fixup_ports(); + } + + void find_same_cells() + { + SigMap assign_map(equiv_mod); + + for (auto id : cell_names) + { + IdString gold_id = id.str() + "_gold"; + IdString gate_id = id.str() + "_gate"; + + Cell *gold_cell = equiv_mod->cell(gold_id); + Cell *gate_cell = equiv_mod->cell(gate_id); + + if (gold_cell == nullptr || gate_cell == nullptr || gold_cell->type != gate_cell->type || !ct.cell_known(gold_cell->type) || + gold_cell->parameters != gate_cell->parameters || GetSize(gold_cell->connections()) != GetSize(gate_cell->connections())) + try_next_cell_name: + continue; + + for (auto gold_conn : gold_cell->connections()) + if (!gate_cell->connections().count(gold_conn.first)) + goto try_next_cell_name; + + log("Presumably equivalent cells: %s %s (%s) -> %s\n", + gold_cell, gate_cell, gold_cell->type.unescape(), id.unescape()); + + for (auto gold_conn : gold_cell->connections()) + { + SigSpec gold_sig = assign_map(gold_conn.second); + SigSpec gate_sig = assign_map(gate_cell->getPort(gold_conn.first)); + + if (ct.cell_output(gold_cell->type, gold_conn.first)) { + equiv_mod->connect(gate_sig, gold_sig); + continue; + } + + if (make_assert) + { + if (gold_sig != gate_sig) + add_eq_assertion(gold_sig, gate_sig); + } + else + { + for (int i = 0; i < GetSize(gold_sig); i++) + if (gold_sig[i] != gate_sig[i]) { + Wire *w = equiv_mod->addWire(NEW_ID); + equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w); + gold_sig[i] = w; + } + } + + gold_cell->setPort(gold_conn.first, gold_sig); + } + + equiv_mod->remove(gate_cell); + equiv_mod->rename(gold_cell, id); + } + } + + void find_undriven_nets(bool mark) + { + undriven_bits.clear(); + assign_map.set(equiv_mod); + + for (auto wire : equiv_mod->wires()) { + for (auto bit : assign_map(wire)) + if (bit.wire) + undriven_bits.insert(bit); + } + + for (auto wire : equiv_mod->wires()) { + if (wire->port_input) + for (auto bit : assign_map(wire)) + undriven_bits.erase(bit); + } + + for (auto cell : equiv_mod->cells()) { + for (auto &conn : cell->connections()) + if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first)) + for (auto bit : assign_map(conn.second)) + undriven_bits.erase(bit); + } + + if (mark) { + SigSpec undriven_sig(undriven_bits); + undriven_sig.sort_and_unify(); + + for (auto chunk : undriven_sig.chunks()) { + log("Setting undriven nets to undef: %s\n", log_signal(chunk)); + equiv_mod->connect(chunk, SigSpec(State::Sx, chunk.width)); + } + } + } + + void run() + { + copy_to_equiv(); + find_undriven_nets(false); + find_same_wires(); + find_same_cells(); + find_undriven_nets(true); + } +}; + +struct EquivMakePass : public Pass { + EquivMakePass() : Pass("equiv_make", "prepare a circuit for equivalence checking") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" equiv_make [options] gold_module gate_module equiv_module\n"); + log("\n"); + log("This creates a module annotated with $equiv cells from two presumably\n"); + log("equivalent modules. Use commands such as 'equiv_simple' and 'equiv_status'\n"); + log("to work with the created equivalent checking module.\n"); + log("\n"); + log(" -inames\n"); + log(" Also match cells and wires with $... names.\n"); + log("\n"); + log(" -blacklist \n"); + log(" Do not match cells or signals that match the names in the file.\n"); + log("\n"); + log(" -encfile \n"); + log(" Match FSM encodings using the description from the file.\n"); + log(" See 'help fsm_recode' for details.\n"); + log("\n"); + log(" -make_assert\n"); + log(" Check equivalence with $assert cells instead of $equiv.\n"); + log(" $eqx (===) is used to compare signals."); + log("\n"); + log("Note: The circuit created by this command is not a miter (with something like\n"); + log("a trigger output), but instead uses $equiv cells to encode the equivalence\n"); + log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) override + { + EquivMakeWorker worker; + worker.ct.setup(design); + worker.inames = false; + worker.make_assert = false; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-inames") { + worker.inames = true; + continue; + } + if (args[argidx] == "-blacklist" && argidx+1 < args.size()) { + worker.blacklists.push_back(args[++argidx]); + continue; + } + if (args[argidx] == "-encfile" && argidx+1 < args.size()) { + worker.encfiles.push_back(args[++argidx]); + continue; + } + if (args[argidx] == "-make_assert") { + worker.make_assert = true; + continue; + } + break; + } + + if (argidx+3 != args.size()) + log_cmd_error("Invalid number of arguments.\n"); + + worker.gold_mod = design->module(RTLIL::escape_id(args[argidx])); + worker.gate_mod = design->module(RTLIL::escape_id(args[argidx+1])); + worker.equiv_mod = design->module(RTLIL::escape_id(args[argidx+2])); + + if (worker.gold_mod == nullptr) + log_cmd_error("Can't find gold module %s.\n", args[argidx]); + + if (worker.gate_mod == nullptr) + log_cmd_error("Can't find gate module %s.\n", args[argidx+1]); + + if (worker.equiv_mod != nullptr) + log_cmd_error("Equiv module %s already exists.\n", args[argidx+2]); + + if (worker.gold_mod->has_memories() || worker.gold_mod->has_processes()) + log_cmd_error("Gold module contains memories or processes. Run 'memory' or 'proc' respectively.\n"); + + if (worker.gate_mod->has_memories() || worker.gate_mod->has_processes()) + log_cmd_error("Gate module contains memories or processes. Run 'memory' or 'proc' respectively.\n"); + + worker.read_blacklists(); + worker.read_encfiles(); + + log_header(design, "Executing EQUIV_MAKE pass (creating equiv checking module).\n"); + + worker.equiv_mod = design->addModule(RTLIL::escape_id(args[argidx+2])); + worker.run(); + } +} EquivMakePass; + +PRIVATE_NAMESPACE_END diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index b32c01c39..aa96ec6de 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -39,7 +39,7 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData & for (int i = fsm_data.state_bits-1; i >= 0; i--) fprintf(f, " %s_reg[%d]", name[0] == '\\' ? name.substr(1).c_str() : name.c_str(), i); fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n", prefix, RTLIL::unescape_id(name).c_str(), - prefix, RTLIL::unescape_id(module->name).c_str()); + prefix, module->name.unescape().c_str()); fprintf(f, "set_fsm_encoding {"); for (int i = 0; i < GetSize(fsm_data.state_table); i++) { @@ -49,7 +49,7 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData & } fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n", prefix, RTLIL::unescape_id(name).c_str(), - prefix, RTLIL::unescape_id(module->name).c_str()); + prefix, module->name.unescape().c_str()); } static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fsm_file, FILE *encfile, std::string default_encoding) diff --git a/passes/hierarchy/flatten.cc b/passes/hierarchy/flatten.cc index 2dd20302c..29e7205ee 100644 --- a/passes/hierarchy/flatten.cc +++ b/passes/hierarchy/flatten.cc @@ -281,13 +281,13 @@ struct FlattenWorker if (attr.first == ID::hdlname) scopeinfo->attributes.insert(attr); else - scopeinfo->attributes.emplace(stringf("\\cell_%s", RTLIL::unescape_id(attr.first)), attr.second); + scopeinfo->attributes.emplace(stringf("\\cell_%s", attr.first.unescape()), attr.second); } for (auto const &attr : tpl->attributes) - scopeinfo->attributes.emplace(stringf("\\module_%s", RTLIL::unescape_id(attr.first)), attr.second); + scopeinfo->attributes.emplace(stringf("\\module_%s", attr.first.unescape()), attr.second); - scopeinfo->attributes.emplace(ID(module), RTLIL::unescape_id(tpl->name)); + scopeinfo->attributes.emplace(ID(module), tpl->name.unescape()); } module->remove(cell); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index f41c19672..4580f14be 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -50,7 +50,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, if (cell->type.begins_with("$") && !cell->type.begins_with("$__")) continue; for (auto &pattern : celltypes) - if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str())) + if (patmatch(pattern.c_str(), cell->type.unescape().c_str())) found_celltypes.insert(cell->type); } @@ -100,7 +100,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, while (portnames.size() > 0) { RTLIL::IdString portname = *portnames.begin(); for (auto &decl : portdecls) - if (decl.index == 0 && patmatch(decl.portname.c_str(), RTLIL::unescape_id(portname).c_str())) { + if (decl.index == 0 && patmatch(decl.portname.c_str(), portname.unescape().c_str())) { generate_port_decl_t d = decl; d.portname = portname.str(); d.index = *indices.begin(); @@ -397,7 +397,7 @@ RTLIL::Module *get_module(RTLIL::Design &design, }; for (auto &ext : extensions_list) { - std::string filename = dir + "/" + RTLIL::unescape_id(cell.type) + ext.first; + std::string filename = dir + "/" + cell.type.unescape() + ext.first; if (!check_file_exists(filename)) continue; diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index 6c4023a6a..2680252a7 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -159,7 +159,7 @@ struct CutpointPass : public Pass { if (attr.first == ID::hdlname) scopeinfo->attributes.insert(attr); else - scopeinfo->attributes.emplace(stringf("\\cell_%s", RTLIL::unescape_id(attr.first)), attr.second); + scopeinfo->attributes.emplace(stringf("\\cell_%s", attr.first.unescape()), attr.second); } } diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index b5f2a437c..e84bd9e89 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -632,7 +632,7 @@ struct ExposePass : public Pass { if (!p->port_input && !p->port_output) continue; - RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + RTLIL::unescape_id(p->name), p->width); + RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + p->name.unescape(), p->width); if (p->port_input) w->port_output = true; if (p->port_output) @@ -654,7 +654,7 @@ struct ExposePass : public Pass { { for (auto &it : cell->connections()) { - RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + RTLIL::unescape_id(it.first), it.second.size()); + RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + it.first.unescape(), it.second.size()); if (ct.cell_input(cell->type, it.first)) w->port_output = true; if (ct.cell_output(cell->type, it.first)) diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 9df88b304..5dd1b07b4 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -143,7 +143,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: { if (gold_cross_ports.count(gold_wire)) { - SigSpec w = miter_module->addWire("\\cross_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width); + SigSpec w = miter_module->addWire("\\cross_" + gold_wire->name.unescape(), gold_wire->width); gold_cell->setPort(gold_wire->name, w); if (flag_ignore_gold_x) { RTLIL::SigSpec w_x = miter_module->addWire(NEW_ID, GetSize(w)); @@ -159,7 +159,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: if (gold_wire->port_input) { - RTLIL::Wire *w = miter_module->addWire("\\in_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width); + RTLIL::Wire *w = miter_module->addWire("\\in_" + gold_wire->name.unescape(), gold_wire->width); w->port_input = true; gold_cell->setPort(gold_wire->name, w); @@ -168,10 +168,10 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: if (gold_wire->port_output) { - RTLIL::Wire *w_gold = miter_module->addWire("\\gold_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width); + RTLIL::Wire *w_gold = miter_module->addWire("\\gold_" + gold_wire->name.unescape(), gold_wire->width); w_gold->port_output = flag_make_outputs; - RTLIL::Wire *w_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width); + RTLIL::Wire *w_gate = miter_module->addWire("\\gate_" + gold_wire->name.unescape(), gold_wire->width); w_gate->port_output = flag_make_outputs; gold_cell->setPort(gold_wire->name, w_gold); @@ -244,7 +244,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: if (flag_make_outcmp) { - RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + RTLIL::unescape_id(gold_wire->name)); + RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + gold_wire->name.unescape()); w_cmp->port_output = true; miter_module->connect(RTLIL::SigSig(w_cmp, this_condition)); } @@ -252,7 +252,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: if (flag_make_cover) { auto cover_condition = miter_module->Not(NEW_ID, this_condition); - miter_module->addCover("\\cover_" + RTLIL::unescape_id(gold_wire->name), cover_condition, State::S1); + miter_module->addCover("\\cover_" + gold_wire->name.unescape(), cover_condition, State::S1); } all_conditions.append(this_condition); diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 23af70fa5..3de13cc1a 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -275,9 +275,9 @@ struct SimInstance } if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) { - fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); + fstHandle id = shared->fst->getHandle(scope + "." + wire->name.unescape()); if (id==0 && wire->name.isPublic()) - log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name))); + log_warning("Unable to find wire %s in input file.\n", (scope + "." + wire->name.unescape())); fst_handles[wire] = id; } @@ -316,7 +316,7 @@ struct SimInstance Module *mod = module->design->module(cell->type); if (mod != nullptr) { - dirty_children.insert(new SimInstance(shared, scope + "." + RTLIL::unescape_id(cell->name), mod, cell, this)); + dirty_children.insert(new SimInstance(shared, scope + "." + cell->name.unescape(), mod, cell, this)); } for (auto &port : cell->connections()) { @@ -1209,7 +1209,7 @@ struct SimInstance } } if (!found) - log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(sig_y.as_wire()->name))); + log_error("Unable to find required '%s' signal in file\n",(scope + "." + sig_y.as_wire()->name.unescape())); } } } @@ -1495,7 +1495,7 @@ struct SimWorker : SimShared log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module); if (!w->port_input) log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module); - fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname)); + fstHandle id = fst->getHandle(scope + "." + portname.unescape()); if (id==0) log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape()); fst_clock.push_back(id); @@ -1507,7 +1507,7 @@ struct SimWorker : SimShared log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module); if (!w->port_input) log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module); - fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname)); + fstHandle id = fst->getHandle(scope + "." + portname.unescape()); if (id==0) log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape()); fst_clock.push_back(id); @@ -1517,9 +1517,9 @@ struct SimWorker : SimShared for (auto wire : topmod->wires()) { if (wire->port_input) { - fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); + fstHandle id = fst->getHandle(scope + "." + wire->name.unescape()); if (id==0) - log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name))); + log_error("Unable to find required '%s' signal in file\n",(scope + "." + wire->name.unescape())); top->fst_inputs[wire] = id; } } @@ -2114,12 +2114,12 @@ struct SimWorker : SimShared std::stringstream f; if (wire->width==1) - f << stringf("%s", RTLIL::unescape_id(wire->name)); + f << stringf("%s", wire); else if (wire->upto) - f << stringf("[%d:%d] %s", wire->start_offset, wire->width - 1 + wire->start_offset, RTLIL::unescape_id(wire->name)); + f << stringf("[%d:%d] %s", wire->start_offset, wire->width - 1 + wire->start_offset, wire); else - f << stringf("[%d:%d] %s", wire->width - 1 + wire->start_offset, wire->start_offset, RTLIL::unescape_id(wire->name)); + f << stringf("[%d:%d] %s", wire->width - 1 + wire->start_offset, wire->start_offset, wire); return f.str(); } @@ -2127,7 +2127,7 @@ struct SimWorker : SimShared { std::stringstream f; for(auto item=signals.begin();item!=signals.end();item++) - f << stringf("%c%s", (item==signals.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name)); + f << stringf("%c%s", (item==signals.begin() ? ' ' : ','), item->first); return f.str(); } @@ -2151,7 +2151,7 @@ struct SimWorker : SimShared log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module); if (!w->port_input) log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module); - fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname)); + fstHandle id = fst->getHandle(scope + "." + portname.unescape()); if (id==0) log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape()); fst_clock.push_back(id); @@ -2164,7 +2164,7 @@ struct SimWorker : SimShared log_error("Can't find port %s on module %s.\n", portname.unescape(), top->module); if (!w->port_input) log_error("Clock port %s on module %s is not input.\n", portname.unescape(), top->module); - fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname)); + fstHandle id = fst->getHandle(scope + "." + portname.unescape()); if (id==0) log_error("Can't find port %s.%s in FST.\n", scope, portname.unescape()); fst_clock.push_back(id); @@ -2176,9 +2176,9 @@ struct SimWorker : SimShared std::map outputs; for (auto wire : topmod->wires()) { - fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); + fstHandle id = fst->getHandle(scope + "." + wire->name.unescape()); if (id==0 && (wire->port_input || wire->port_output)) - log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name))); + log_error("Unable to find required '%s' signal in file\n",(scope + "." + wire->name.unescape())); if (wire->port_input) if (clocks.find(wire)==clocks.end()) inputs[wire] = id; @@ -2244,13 +2244,13 @@ struct SimWorker : SimShared } int data_len = clk_len + inputs_len + outputs_len + 32; f << "\n"; - f << stringf("\t%s uut(",RTLIL::unescape_id(topmod->name)); + f << stringf("\t%s uut(",topmod); for(auto item=clocks.begin();item!=clocks.end();item++) - f << stringf("%c.%s(%s)", (item==clocks.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name), RTLIL::unescape_id(item->first->name)); + f << stringf("%c.%s(%s)", (item==clocks.begin() ? ' ' : ','), item->first, item->first); for(auto &item : inputs) - f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name), RTLIL::unescape_id(item.first->name)); + f << stringf(",.%s(%s)", item.first, item.first); for(auto &item : outputs) - f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name), RTLIL::unescape_id(item.first->name)); + f << stringf(",.%s(%s)", item.first, item.first); f << ");\n"; f << "\n"; f << "\tinteger i;\n"; diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 7742fa989..5e804922c 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1565,7 +1565,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL { if (builtin_lib) { - cell_stats[RTLIL::unescape_id(c->type)]++; + cell_stats[c->type.unescape()]++; if (c->type.in(ID(ZERO), ID(ONE))) { RTLIL::SigSig conn; RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name); @@ -1706,7 +1706,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL } } else - cell_stats[RTLIL::unescape_id(c->type)]++; + cell_stats[c->type.unescape()]++; if (c->type.in(ID(_const0_), ID(_const1_))) { RTLIL::SigSig conn; diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index d4d13d673..f63123a23 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -626,7 +626,7 @@ struct ExtractPass : public Pass { if (!mine_mode) for (auto module : map->modules()) { SubCircuit::Graph mod_graph; - std::string graph_name = "needle_" + RTLIL::unescape_id(module->name); + std::string graph_name = "needle_" + module->name.unescape(); log("Creating needle graph %s.\n", graph_name); if (module2graph(mod_graph, module, constports)) { solver.addGraph(graph_name, mod_graph); @@ -637,7 +637,7 @@ struct ExtractPass : public Pass { for (auto module : design->modules()) { SubCircuit::Graph mod_graph; - std::string graph_name = "haystack_" + RTLIL::unescape_id(module->name); + std::string graph_name = "haystack_" + module->name.unescape(); log("Creating haystack graph %s.\n", graph_name); if (module2graph(mod_graph, module, constports, design, mine_mode ? mine_max_fanout : -1, mine_mode ? &mine_split : nullptr)) { solver.addGraph(graph_name, mod_graph); @@ -654,8 +654,8 @@ struct ExtractPass : public Pass { for (auto needle : needle_list) for (auto &haystack_it : haystack_map) { - log("Solving for %s in %s.\n", ("needle_" + RTLIL::unescape_id(needle->name)), haystack_it.first); - solver.solve(results, "needle_" + RTLIL::unescape_id(needle->name), haystack_it.first, false); + log("Solving for %s in %s.\n", ("needle_" + needle->name.unescape()), haystack_it.first); + solver.solve(results, "needle_" + needle->name.unescape(), haystack_it.first, false); } log("Found %d matches.\n", GetSize(results)); diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index e975d2fd2..984926be8 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -616,9 +616,9 @@ struct TechmapWorker } if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0) - parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type)); + parameters.emplace(ID::_TECHMAP_CELLTYPE_, cell->type.unescape()); if (tpl->avail_parameters.count(ID::_TECHMAP_CELLNAME_) != 0) - parameters.emplace(ID::_TECHMAP_CELLNAME_, RTLIL::unescape_id(cell->name)); + parameters.emplace(ID::_TECHMAP_CELLNAME_, cell->name.unescape()); for (auto &conn : cell->connections()) { if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", conn.first.unescape())) != 0) { diff --git a/techlibs/common/opensta.cc b/techlibs/common/opensta.cc index 655fdbf2d..6061f6b74 100644 --- a/techlibs/common/opensta.cc +++ b/techlibs/common/opensta.cc @@ -98,7 +98,7 @@ struct OpenstaPass : public Pass f_script << "read_verilog " << verilog_filename << "\n"; f_script << "read_lib " << liberty_filename << "\n"; - f_script << "link_design " << RTLIL::unescape_id(top_mod->name) << "\n"; + f_script << "link_design " << top_mod->name.unescape() << "\n"; f_script << "read_sdc " << sdc_filename << "\n"; f_script << "write_sdc " << sdc_expanded_filename << "\n"; f_script.close(); From ef092e1f15a205d027cd0e03279ec580c8071a33 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 18 May 2026 08:50:20 +0200 Subject: [PATCH 08/30] Include conf so individual test running works --- tests/gen_tests_makefile.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/gen_tests_makefile.py b/tests/gen_tests_makefile.py index 38596f63b..e4e44241c 100644 --- a/tests/gen_tests_makefile.py +++ b/tests/gen_tests_makefile.py @@ -94,6 +94,9 @@ def generate_tests(argv, cmds): def print_header(extra=None): print(f"include {common_mk}") + print(f"ifneq ($(wildcard {yosys_basedir}/Makefile.conf),)") + print(f"include {yosys_basedir}/Makefile.conf") + print(f"endif") print(f"YOSYS ?= {yosys_basedir}/yosys") print("") print("export YOSYS_MAX_THREADS := 4") From 4a4c3a3be616098a34ae4079b24e501dcfbb7130 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 18 May 2026 08:50:38 +0200 Subject: [PATCH 09/30] Make better validation --- tests/memories/generate_mk.py | 48 +------------- tests/memories/validate.py | 116 ++++++++++++++++++++++++++++++++++ 2 files changed, 117 insertions(+), 47 deletions(-) create mode 100644 tests/memories/validate.py diff --git a/tests/memories/generate_mk.py b/tests/memories/generate_mk.py index cfb29acb9..93a5bec04 100644 --- a/tests/memories/generate_mk.py +++ b/tests/memories/generate_mk.py @@ -8,51 +8,5 @@ import gen_tests_makefile gen_tests_makefile.generate_autotest("*.v", "", """if grep -Eq 'expect-(wr-ports|rd-ports|rd-clk)' $@; then \\ $(YOSYS) -f verilog -qp "proc; opt; memory -nomap; dump -outfile $(@:.v=).dmp t:\\$$mem_v2" $@; \\ - if grep -q expect-wr-ports $@; then \\ - val=$$(gawk '/expect-wr-ports/ { print $$3; }' $@); \\ - grep -Fq "parameter \\\\WR_PORTS $$val" $(@:.v=).dmp || { echo " ERROR: Unexpected number of write ports."; exit 1; }; \\ - fi; \\ - if grep -q expect-wr-wide-continuation $@; then \\ - val=$$(gawk '/expect-wr-wide-continuation/ { print $$3; }' $@); \\ - grep -Fq "parameter \\\\WR_WIDE_CONTINUATION $$val" $(@:.v=).dmp || { echo " ERROR: Unexpected write wide continuation."; exit 1; }; \\ - fi; \\ - if grep -q expect-rd-ports $@; then \\ - val=$$(gawk '/expect-rd-ports/ { print $$3; }' $@); \\ - grep -Fq "parameter \\\\RD_PORTS $$val" $(@:.v=).dmp || { echo " ERROR: Unexpected number of read ports."; exit 1; }; \\ - fi; \\ - if grep -q expect-rd-clk $@; then \\ - val=$$(gawk '/expect-rd-clk/ { print $$3; }' $@); \\ - grep -Fq "connect \\\\RD_CLK $$val" $(@:.v=).dmp || { echo " ERROR: Unexpected read clock."; exit 1; }; \\ - fi; \\ - if grep -q expect-rd-en $@; then \\ - val=$$(gawk '/expect-rd-en/ { print $$3; }' $@); \\ - grep -Fq "connect \\\\RD_EN $$val" $(@:.v=).dmp || { echo " ERROR: Unexpected read enable."; exit 1; }; \\ - fi; \\ - if grep -q expect-rd-srst-sig $@; then \\ - val=$$(gawk '/expect-rd-srst-sig/ { print $$3; }' $@); \\ - grep -Fq "connect \\\\RD_SRST $$val" $(@:.v=).dmp || { echo " ERROR: Unexpected read sync reset."; exit 1; }; \\ - fi; \\ - if grep -q expect-rd-srst-val $@; then \\ - val=$$(gawk '/expect-rd-srst-val/ { print $$3; }' $@); \\ - grep -Fq "parameter \\\\RD_SRST_VALUE $$val" $(@:.v=).dmp || { echo " ERROR: Unexpected read sync reset value."; exit 1; }; \\ - fi; \\ - if grep -q expect-rd-arst-sig $@; then \\ - val=$$(gawk '/expect-rd-arst-sig/ { print $$3; }' $@); \\ - grep -Fq "connect \\\\RD_ARST $$val" $(@:.v=).dmp || { echo " ERROR: Unexpected read async reset."; exit 1; }; \\ - fi; \\ - if grep -q expect-rd-arst-val $@; then \\ - val=$$(gawk '/expect-rd-arst-val/ { print $$3; }' $@); \\ - grep -Fq "parameter \\\\RD_ARST_VALUE $$val" $(@:.v=).dmp || { echo " ERROR: Unexpected read async reset value."; exit 1; }; \\ - fi; \\ - if grep -q expect-rd-init-val $@; then \\ - val=$$(gawk '/expect-rd-init-val/ { print $$3; }' $@); \\ - grep -Fq "parameter \\\\RD_INIT_VALUE $$val" $(@:.v=).dmp || { echo " ERROR: Unexpected read init value."; exit 1; }; \\ - fi; \\ - if grep -q expect-rd-wide-continuation $@; then \\ - val=$$(gawk '/expect-rd-wide-continuation/ { print $$3; }' $@); \\ - grep -Fq "parameter \\\\RD_WIDE_CONTINUATION $$val" $(@:.v=).dmp || { echo " ERROR: Unexpected read wide continuation."; exit 1; }; \\ - fi; \\ - if grep -q expect-no-rd-clk $@; then \\ - grep -Fq "connect \\\\RD_CLK 1'x" $(@:.v=).dmp || { echo " ERROR: Expected no read clock."; exit 1; }; \\ - fi; \\ + python3 validate.py $@ $(@:.v=).dmp; \\ fi""") diff --git a/tests/memories/validate.py b/tests/memories/validate.py new file mode 100644 index 000000000..88aabdd49 --- /dev/null +++ b/tests/memories/validate.py @@ -0,0 +1,116 @@ +#!/usr/bin/env python3 +import re +import sys +from pathlib import Path + +CHECKS = [ + ( + "expect-wr-ports", + r"parameter \\WR_PORTS {val}$", + "ERROR: Unexpected number of write ports.", + ), + ( + "expect-wr-wide-continuation", + r"parameter \\WR_WIDE_CONTINUATION {val}$", + "ERROR: Unexpected write wide continuation.", + ), + ( + "expect-rd-ports", + r"parameter \\RD_PORTS {val}$", + "ERROR: Unexpected number of read ports.", + ), + ( + "expect-rd-clk", + r"connect \\RD_CLK {val}$", + "ERROR: Unexpected read clock.", + ), + ( + "expect-rd-en", + r"connect \\RD_EN {val}$", + "ERROR: Unexpected read enable.", + ), + ( + "expect-rd-srst-sig", + r"connect \\RD_SRST {val}$", + "ERROR: Unexpected read sync reset.", + ), + ( + "expect-rd-srst-val", + r"parameter \\RD_SRST_VALUE {val}$", + "ERROR: Unexpected read sync reset value.", + ), + ( + "expect-rd-arst-sig", + r"connect \\RD_ARST {val}$", + "ERROR: Unexpected read async reset.", + ), + ( + "expect-rd-arst-val", + r"parameter \\RD_ARST_VALUE {val}$", + "ERROR: Unexpected read async reset value.", + ), + ( + "expect-rd-init-val", + r"parameter \\RD_INIT_VALUE {val}$", + "ERROR: Unexpected read init value.", + ), + ( + "expect-rd-wide-continuation", + r"parameter \\RD_WIDE_CONTINUATION {val}$", + "ERROR: Unexpected read wide continuation.", + ), + ( + "expect-no-rd-clk", + r"connect \\RD_CLK 1'x$", + "ERROR: Expected no read clock.", + ), +] + + +def extract_expect_value(src_text: str, key: str): + pattern = rf"{re.escape(key)}\s+(\S+)" + m = re.search(pattern, src_text) + return m.group(1) if m else None + + +def main(): + if len(sys.argv) != 3: + print(f"Usage: {sys.argv[0]} ", file=sys.stderr) + return 2 + + srcfile = Path(sys.argv[1]) + dmpfile = Path(sys.argv[2]) + + try: + src_text = srcfile.read_text() + except Exception as e: + print(f"ERROR: Failed to read {srcfile}: {e}", file=sys.stderr) + return 2 + + try: + dmp_text = dmpfile.read_text() + except Exception as e: + print(f"ERROR: Failed to read {dmpfile}: {e}", file=sys.stderr) + return 2 + + for key, pattern_template, errmsg in CHECKS: + if "{val}" in pattern_template: + val = extract_expect_value(src_text, key) + if val is None: + continue + pattern = pattern_template.format(val=re.escape(val)) + else: + if key not in src_text: + continue + pattern = pattern_template + + if not re.search(pattern, dmp_text, re.MULTILINE): + print(errmsg, file=sys.stderr) + return 1 + + print("ok.") + return 0 + + +if __name__ == "__main__": + sys.exit(main()) From 35d13e1c3268884791b47ee6f567775ec669ae14 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 18 May 2026 09:13:46 +0200 Subject: [PATCH 10/30] Update documentation/demos based on cleanup --- docs/source/code_examples/functional/dummy.cc | 14 +++++++------- .../yosys_internals/extending_yosys/extensions.rst | 3 +-- .../extending_yosys/functional_ir.rst | 2 +- 3 files changed, 9 insertions(+), 10 deletions(-) diff --git a/docs/source/code_examples/functional/dummy.cc b/docs/source/code_examples/functional/dummy.cc index 42b05b339..a339bc275 100644 --- a/docs/source/code_examples/functional/dummy.cc +++ b/docs/source/code_examples/functional/dummy.cc @@ -24,19 +24,19 @@ struct FunctionalDummyBackend : public Backend { // write node functions for (auto node : ir) - *f << " assign " << id2cstr(node.name()) + *f << " assign " << node.name().unescape() << " = " << node.to_string() << "\n"; *f << "\n"; // write outputs and next state for (auto output : ir.outputs()) - *f << " " << id2cstr(output->kind) - << " " << id2cstr(output->name) - << " = " << id2cstr(output->value().name()) << "\n"; + *f << " " << output->kind.unescape() + << " " << output->name.unescape() + << " = " << output->value().name().unescape() << "\n"; for (auto state : ir.states()) - *f << " " << id2cstr(state->kind) - << " " << id2cstr(state->name) - << " = " << id2cstr(state->next_value().name()) << "\n"; + *f << " " << state->kind.unescape() + << " " << state->name.unescape() + << " = " << state->next_value().name().unescape() << "\n"; } } } FunctionalDummyBackend; diff --git a/docs/source/yosys_internals/extending_yosys/extensions.rst b/docs/source/yosys_internals/extending_yosys/extensions.rst index 74a7d72d6..949c78586 100644 --- a/docs/source/yosys_internals/extending_yosys/extensions.rst +++ b/docs/source/yosys_internals/extending_yosys/extensions.rst @@ -230,8 +230,7 @@ Use ``log_error()`` to report a non-recoverable error: .. code:: C++ if (design->modules.count(module->name) != 0) - log_error("A module with the name %s already exists!\n", - RTLIL::id2cstr(module->name)); + log_error("A module with the name %s already exists!\n", module); Use ``log_cmd_error()`` to report a recoverable error: diff --git a/docs/source/yosys_internals/extending_yosys/functional_ir.rst b/docs/source/yosys_internals/extending_yosys/functional_ir.rst index 4f363623e..1c4ab5281 100644 --- a/docs/source/yosys_internals/extending_yosys/functional_ir.rst +++ b/docs/source/yosys_internals/extending_yosys/functional_ir.rst @@ -181,7 +181,7 @@ pointer ``f`` to the output file, or stdout if none is given. For this minimal example all we are doing is printing out each node. The ``node.name()`` method returns an ``RTLIL::IdString``, which we convert for -printing with ``id2cstr()``. Then, to print the function of the node, we use +printing with ``unescape()``. Then, to print the function of the node, we use ``node.to_string()`` which gives us a string of the form ``function(args)``. The ``function`` part is the result of ``Functional::IR::fn_to_string(node.fn())``; while ``args`` is the zero or more arguments passed to the function, most From d322e2fbe0369fe58163c5e336469c142b9632e5 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 12 May 2026 11:43:32 +0200 Subject: [PATCH 11/30] threading: redirect locks to no-op when ENABLE_THREADS=0 or undefined YOSYS_ENABLE_THREADS --- kernel/threading.cc | 14 +++--- kernel/threading.h | 105 +++++++++++++++++++++++--------------------- 2 files changed, 60 insertions(+), 59 deletions(-) diff --git a/kernel/threading.cc b/kernel/threading.cc index eda6bb4cb..a49ee7d4e 100644 --- a/kernel/threading.cc +++ b/kernel/threading.cc @@ -70,7 +70,7 @@ ThreadPool::ThreadPool(int pool_size, std::function b) for (int i = 0; i < pool_size; i++) threads.emplace_back([i, this]{ body(i); }); #else - log_assert(pool_size == 0); + (void)pool_size; #endif } @@ -96,11 +96,13 @@ IntRange item_range_for_worker(int num_items, int thread_num, int num_threads) } ParallelDispatchThreadPool::ParallelDispatchThreadPool(int pool_size) - : num_worker_threads_(std::max(1, pool_size) - 1) -{ #ifdef YOSYS_ENABLE_THREADS - main_to_workers_signal.resize(num_worker_threads_, 0); + : num_worker_threads_(std::max(1, pool_size) - 1) +#else + : num_worker_threads_(0) #endif +{ + main_to_workers_signal.resize(num_worker_threads_, 0); // Don't start the threads until we've constructed all our data members. thread_pool = std::make_unique(num_worker_threads_, [this](int thread_num){ run_worker(thread_num); @@ -109,14 +111,12 @@ ParallelDispatchThreadPool::ParallelDispatchThreadPool(int pool_size) ParallelDispatchThreadPool::~ParallelDispatchThreadPool() { -#ifdef YOSYS_ENABLE_THREADS if (num_worker_threads_ == 0) return; current_work = nullptr; num_active_worker_threads_.store(num_worker_threads_, std::memory_order_relaxed); signal_workers_start(); wait_for_workers_done(); -#endif } void ParallelDispatchThreadPool::run(std::function work, int max_threads) @@ -127,13 +127,11 @@ void ParallelDispatchThreadPool::run(std::function work, i work({{0}, 1}); return; } -#ifdef YOSYS_ENABLE_THREADS num_active_worker_threads_.store(num_active_worker_threads, std::memory_order_relaxed); current_work = &work; signal_workers_start(); work({{0}, num_active_worker_threads + 1}); wait_for_workers_done(); -#endif } void ParallelDispatchThreadPool::run_worker(int thread_num) diff --git a/kernel/threading.h b/kernel/threading.h index 3a31b0633..98d3068c4 100644 --- a/kernel/threading.h +++ b/kernel/threading.h @@ -15,6 +15,33 @@ YOSYS_NAMESPACE_BEGIN +// Redirect to no-op to avoid dependence on +// and in single-threaded builds +#ifdef YOSYS_ENABLE_THREADS +using Mutex = std::mutex; +using CondVar = std::condition_variable; +template using UniqueLock = std::unique_lock; +template using LockGuard = std::lock_guard; +#else +struct Mutex { + void lock() {} + void unlock() {} + bool try_lock() { return true; } +}; +struct CondVar { + template void wait(L &) {} + template void wait(L &, P) {} + void notify_one() {} + void notify_all() {} +}; +template struct UniqueLock { + UniqueLock(M &) {} +}; +template struct LockGuard { + LockGuard(M &) {} +}; +#endif + // Concurrent queue implementation. Not fast, but simple. // Multi-producer, multi-consumer, optionally bounded. // When YOSYS_ENABLE_THREADS is not defined, this is just a non-thread-safe non-blocking deque. @@ -27,26 +54,20 @@ public: // Push an element into the queue. If it's at capacity, block until there is room. void push_back(T t) { -#ifdef YOSYS_ENABLE_THREADS - std::unique_lock lock(mutex); + UniqueLock lock(mutex); not_full_condition.wait(lock, [this] { return static_cast(contents.size()) < capacity; }); if (contents.empty()) not_empty_condition.notify_one(); -#endif log_assert(!closed); contents.push_back(std::move(t)); -#ifdef YOSYS_ENABLE_THREADS if (static_cast(contents.size()) < capacity) not_full_condition.notify_one(); -#endif } // Signal that no more elements will be produced. `pop_front()` will return nullopt. void close() { -#ifdef YOSYS_ENABLE_THREADS - std::unique_lock lock(mutex); + UniqueLock lock(mutex); not_empty_condition.notify_all(); -#endif closed = true; } // Pop an element from the queue. Blocks until an element is available @@ -62,39 +83,28 @@ public: return pop_front_internal(false); } private: -#ifdef YOSYS_ENABLE_THREADS std::optional pop_front_internal(bool wait) { - std::unique_lock lock(mutex); + UniqueLock lock(mutex); if (wait) { not_empty_condition.wait(lock, [this] { return !contents.empty() || closed; }); } -#else - std::optional pop_front_internal(bool) - { -#endif if (contents.empty()) return std::nullopt; -#ifdef YOSYS_ENABLE_THREADS if (static_cast(contents.size()) == capacity) not_full_condition.notify_one(); -#endif T result = std::move(contents.front()); contents.pop_front(); -#ifdef YOSYS_ENABLE_THREADS if (!contents.empty()) not_empty_condition.notify_one(); -#endif return std::move(result); } -#ifdef YOSYS_ENABLE_THREADS - std::mutex mutex; + Mutex mutex; // Signals one waiter thread when the queue changes and is not full. - std::condition_variable not_full_condition; + CondVar not_full_condition; // Signals one waiter thread when the queue changes and is not empty. - std::condition_variable not_empty_condition; -#endif + CondVar not_empty_condition; std::deque contents; int capacity; bool closed = false; @@ -245,15 +255,14 @@ private: // is maintained. std::atomic num_active_worker_threads_ = 0; -#ifdef YOSYS_ENABLE_THREADS // Not especially efficient for large numbers of threads. Worker wakeup could scale // better by conceptually organising workers into a tree and having workers wake // up their children. - std::mutex main_to_workers_signal_mutex; - std::condition_variable main_to_workers_signal_cv; + Mutex main_to_workers_signal_mutex; + CondVar main_to_workers_signal_cv; std::vector main_to_workers_signal; void signal_workers_start() { - std::unique_lock lock(main_to_workers_signal_mutex); + UniqueLock lock(main_to_workers_signal_mutex); int num_active_worker_threads = num_active_worker_threads_.load(std::memory_order_relaxed); std::fill(main_to_workers_signal.begin(), main_to_workers_signal.begin() + num_active_worker_threads, 1); // When `num_active_worker_threads_` is small compared to `num_worker_threads_`, we have a "thundering herd" @@ -261,14 +270,14 @@ private: main_to_workers_signal_cv.notify_all(); } void worker_wait_for_start(int thread_num) { - std::unique_lock lock(main_to_workers_signal_mutex); + UniqueLock lock(main_to_workers_signal_mutex); main_to_workers_signal_cv.wait(lock, [this, thread_num] { return main_to_workers_signal[thread_num] > 0; }); main_to_workers_signal[thread_num] = 0; } std::atomic done_workers = 0; - std::mutex workers_to_main_signal_mutex; - std::condition_variable workers_to_main_signal_cv; + Mutex workers_to_main_signal_mutex; + CondVar workers_to_main_signal_cv; void signal_worker_done() { // Must read `num_active_worker_threads_` before we increment `d`! Otherwise // it is possible we would increment `d`, and then another worker signals the @@ -277,19 +286,18 @@ private: int num_active_worker_threads = num_active_worker_threads_.load(std::memory_order_relaxed); int d = done_workers.fetch_add(1, std::memory_order_release); if (d + 1 == num_active_worker_threads) { - std::unique_lock lock(workers_to_main_signal_mutex); + UniqueLock lock(workers_to_main_signal_mutex); workers_to_main_signal_cv.notify_all(); } } void wait_for_workers_done() { - std::unique_lock lock(workers_to_main_signal_mutex); + UniqueLock lock(workers_to_main_signal_mutex); workers_to_main_signal_cv.wait(lock, [this] { int num_active_worker_threads = num_active_worker_threads_.load(std::memory_order_relaxed); return done_workers.load(std::memory_order_acquire) == num_active_worker_threads; }); done_workers.store(0, std::memory_order_relaxed); } -#endif // Ensure `thread_pool` is destroyed before any other members, // forcing all threads to be joined before destroying the // members (e.g. workers_to_main_signal_mutex) they might be using. @@ -301,15 +309,11 @@ class ConcurrentStack { public: void push_back(T &&t) { -#ifdef YOSYS_ENABLE_THREADS - std::lock_guard lock(mutex); -#endif + LockGuard lock(mutex); contents.push_back(std::move(t)); } std::optional try_pop_back() { -#ifdef YOSYS_ENABLE_THREADS - std::lock_guard lock(mutex); -#endif + LockGuard lock(mutex); if (contents.empty()) return std::nullopt; T result = std::move(contents.back()); @@ -317,9 +321,7 @@ public: return result; } private: -#ifdef YOSYS_ENABLE_THREADS - std::mutex mutex; -#endif + Mutex mutex; std::vector contents; }; @@ -596,12 +598,12 @@ public: return; bool was_empty; { - std::unique_lock lock(thread_state.batches_lock); + UniqueLock lock(thread_state.batches_lock); was_empty = thread_state.batches.empty(); thread_state.batches.push_back(std::move(thread_state.next_batch)); } if (was_empty) { - std::unique_lock lock(waiters_lock); + UniqueLock lock(waiters_lock); if (num_waiters > 0) { waiters_cv.notify_one(); } @@ -617,7 +619,7 @@ public: return std::move(thread_state.next_batch); // Empty our own work queue first. { - std::unique_lock lock(thread_state.batches_lock); + UniqueLock lock(thread_state.batches_lock); if (!thread_state.batches.empty()) { std::vector batch = std::move(thread_state.batches.back()); thread_state.batches.pop_back(); @@ -634,8 +636,9 @@ public: // them will eventually enter this loop and there will be no further // notifications on waiters_cv, so all will eventually increment // num_waiters and wait, so num_waiters == num_threads() - // will become true. - std::unique_lock lock(waiters_lock); + // will become true. In single-threaded builds, num_threads() is 1, + // so we always terminate on the first iteration. + UniqueLock lock(waiters_lock); ++num_waiters; if (num_waiters == num_threads()) { waiters_cv.notify_all(); @@ -654,7 +657,7 @@ private: for (int i = 1; i < num_threads(); i++) { int other_thread_num = (thread.thread_num + i) % num_threads(); ThreadState &other_thread_state = thread_states[other_thread_num]; - std::unique_lock lock(other_thread_state.batches_lock); + UniqueLock lock(other_thread_state.batches_lock); if (!other_thread_state.batches.empty()) { std::vector batch = std::move(other_thread_state.batches.front()); other_thread_state.batches.pop_front(); @@ -670,15 +673,15 @@ private: // Entirely thread-local. std::vector next_batch; - std::mutex batches_lock; + Mutex batches_lock; // Only the associated thread ever adds to this, and only at the back. // Other threads can remove elements from the front. std::deque> batches; }; std::vector thread_states; - std::mutex waiters_lock; - std::condition_variable waiters_cv; + Mutex waiters_lock; + CondVar waiters_cv; // Number of threads waiting for work. Their queues are empty. int num_waiters = 0; }; From 1c831aa50de37556406e10985f94be882210dc92 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 12 May 2026 12:19:06 +0200 Subject: [PATCH 12/30] threading: whitespace --- kernel/threading.cc | 8 ++++---- tests/unit/kernel/threadingTest.cc | 4 +++- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/kernel/threading.cc b/kernel/threading.cc index a49ee7d4e..a334dfa4c 100644 --- a/kernel/threading.cc +++ b/kernel/threading.cc @@ -66,11 +66,11 @@ ThreadPool::ThreadPool(int pool_size, std::function b) : body(std::move(b)) { #ifdef YOSYS_ENABLE_THREADS - threads.reserve(pool_size); - for (int i = 0; i < pool_size; i++) - threads.emplace_back([i, this]{ body(i); }); + threads.reserve(pool_size); + for (int i = 0; i < pool_size; i++) + threads.emplace_back([i, this]{ body(i); }); #else - (void)pool_size; + (void)pool_size; #endif } diff --git a/tests/unit/kernel/threadingTest.cc b/tests/unit/kernel/threadingTest.cc index cbab4d118..4e204fc61 100644 --- a/tests/unit/kernel/threadingTest.cc +++ b/tests/unit/kernel/threadingTest.cc @@ -109,8 +109,10 @@ TEST_F(ThreadingTest, IntRangeIteration) { TEST_F(ThreadingTest, IntRangeEmpty) { IntRange range{5, 5}; - for (int _ : range) + for (int _ : range) { + (void)_; FAIL(); + } } TEST_F(ThreadingTest, ItemRangeForWorker) { From 0c2786be1f34e5bbadcc38e02e8bf291a4d7a21f Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 18 May 2026 16:13:19 +0200 Subject: [PATCH 13/30] threading: make no-op locks specialized to Mutex instead of templates --- kernel/threading.h | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/kernel/threading.h b/kernel/threading.h index 98d3068c4..c843b23ae 100644 --- a/kernel/threading.h +++ b/kernel/threading.h @@ -20,8 +20,8 @@ YOSYS_NAMESPACE_BEGIN #ifdef YOSYS_ENABLE_THREADS using Mutex = std::mutex; using CondVar = std::condition_variable; -template using UniqueLock = std::unique_lock; -template using LockGuard = std::lock_guard; +using UniqueLock = std::unique_lock; +using LockGuard = std::lock_guard; #else struct Mutex { void lock() {} @@ -34,11 +34,11 @@ struct CondVar { void notify_one() {} void notify_all() {} }; -template struct UniqueLock { - UniqueLock(M &) {} +struct UniqueLock { + UniqueLock(Mutex &) {} }; -template struct LockGuard { - LockGuard(M &) {} +struct LockGuard { + LockGuard(Mutex &) {} }; #endif @@ -54,7 +54,7 @@ public: // Push an element into the queue. If it's at capacity, block until there is room. void push_back(T t) { - UniqueLock lock(mutex); + UniqueLock lock(mutex); not_full_condition.wait(lock, [this] { return static_cast(contents.size()) < capacity; }); if (contents.empty()) not_empty_condition.notify_one(); @@ -66,7 +66,7 @@ public: // Signal that no more elements will be produced. `pop_front()` will return nullopt. void close() { - UniqueLock lock(mutex); + UniqueLock lock(mutex); not_empty_condition.notify_all(); closed = true; } @@ -85,7 +85,7 @@ public: private: std::optional pop_front_internal(bool wait) { - UniqueLock lock(mutex); + UniqueLock lock(mutex); if (wait) { not_empty_condition.wait(lock, [this] { return !contents.empty() || closed; }); } @@ -262,7 +262,7 @@ private: CondVar main_to_workers_signal_cv; std::vector main_to_workers_signal; void signal_workers_start() { - UniqueLock lock(main_to_workers_signal_mutex); + UniqueLock lock(main_to_workers_signal_mutex); int num_active_worker_threads = num_active_worker_threads_.load(std::memory_order_relaxed); std::fill(main_to_workers_signal.begin(), main_to_workers_signal.begin() + num_active_worker_threads, 1); // When `num_active_worker_threads_` is small compared to `num_worker_threads_`, we have a "thundering herd" @@ -270,7 +270,7 @@ private: main_to_workers_signal_cv.notify_all(); } void worker_wait_for_start(int thread_num) { - UniqueLock lock(main_to_workers_signal_mutex); + UniqueLock lock(main_to_workers_signal_mutex); main_to_workers_signal_cv.wait(lock, [this, thread_num] { return main_to_workers_signal[thread_num] > 0; }); main_to_workers_signal[thread_num] = 0; } @@ -286,12 +286,12 @@ private: int num_active_worker_threads = num_active_worker_threads_.load(std::memory_order_relaxed); int d = done_workers.fetch_add(1, std::memory_order_release); if (d + 1 == num_active_worker_threads) { - UniqueLock lock(workers_to_main_signal_mutex); + UniqueLock lock(workers_to_main_signal_mutex); workers_to_main_signal_cv.notify_all(); } } void wait_for_workers_done() { - UniqueLock lock(workers_to_main_signal_mutex); + UniqueLock lock(workers_to_main_signal_mutex); workers_to_main_signal_cv.wait(lock, [this] { int num_active_worker_threads = num_active_worker_threads_.load(std::memory_order_relaxed); return done_workers.load(std::memory_order_acquire) == num_active_worker_threads; @@ -309,11 +309,11 @@ class ConcurrentStack { public: void push_back(T &&t) { - LockGuard lock(mutex); + LockGuard lock(mutex); contents.push_back(std::move(t)); } std::optional try_pop_back() { - LockGuard lock(mutex); + LockGuard lock(mutex); if (contents.empty()) return std::nullopt; T result = std::move(contents.back()); @@ -598,12 +598,12 @@ public: return; bool was_empty; { - UniqueLock lock(thread_state.batches_lock); + UniqueLock lock(thread_state.batches_lock); was_empty = thread_state.batches.empty(); thread_state.batches.push_back(std::move(thread_state.next_batch)); } if (was_empty) { - UniqueLock lock(waiters_lock); + UniqueLock lock(waiters_lock); if (num_waiters > 0) { waiters_cv.notify_one(); } @@ -619,7 +619,7 @@ public: return std::move(thread_state.next_batch); // Empty our own work queue first. { - UniqueLock lock(thread_state.batches_lock); + UniqueLock lock(thread_state.batches_lock); if (!thread_state.batches.empty()) { std::vector batch = std::move(thread_state.batches.back()); thread_state.batches.pop_back(); @@ -638,7 +638,7 @@ public: // num_waiters and wait, so num_waiters == num_threads() // will become true. In single-threaded builds, num_threads() is 1, // so we always terminate on the first iteration. - UniqueLock lock(waiters_lock); + UniqueLock lock(waiters_lock); ++num_waiters; if (num_waiters == num_threads()) { waiters_cv.notify_all(); @@ -657,7 +657,7 @@ private: for (int i = 1; i < num_threads(); i++) { int other_thread_num = (thread.thread_num + i) % num_threads(); ThreadState &other_thread_state = thread_states[other_thread_num]; - UniqueLock lock(other_thread_state.batches_lock); + UniqueLock lock(other_thread_state.batches_lock); if (!other_thread_state.batches.empty()) { std::vector batch = std::move(other_thread_state.batches.front()); other_thread_state.batches.pop_front(); From 2159a0e6340a1e2b2adbb5077979c1df43538216 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 18 May 2026 17:00:16 +0200 Subject: [PATCH 14/30] Remove file added by mistake --- passes/equiv/equiv_make.cc.orig | 520 -------------------------------- 1 file changed, 520 deletions(-) delete mode 100644 passes/equiv/equiv_make.cc.orig diff --git a/passes/equiv/equiv_make.cc.orig b/passes/equiv/equiv_make.cc.orig deleted file mode 100644 index 3aa3fac63..000000000 --- a/passes/equiv/equiv_make.cc.orig +++ /dev/null @@ -1,520 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Claire Xenia Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/sigtools.h" -#include "kernel/celltypes.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct EquivMakeWorker -{ - Module *gold_mod, *gate_mod, *equiv_mod; - pool wire_names, cell_names; - CellTypes ct; - - bool inames; - vector blacklists; - vector encfiles; - bool make_assert; - - pool blacklist_names; - dict> encdata; - - pool undriven_bits; - SigMap assign_map; - - void read_blacklists() - { - for (auto fn : blacklists) - { - std::ifstream f(fn); - if (f.fail()) - log_cmd_error("Can't open blacklist file '%s'!\n", fn); - - string line, token; - while (std::getline(f, line)) { - while (1) { - token = next_token(line); - if (token.empty()) - break; - blacklist_names.insert(RTLIL::escape_id(token)); - } - } - } - } - - void read_encfiles() - { - for (auto fn : encfiles) - { - std::ifstream f(fn); - if (f.fail()) - log_cmd_error("Can't open encfile '%s'!\n", fn); - - dict *ed = nullptr; - string line, token; - while (std::getline(f, line)) - { - token = next_token(line); - if (token.empty() || token[0] == '#') - continue; - - if (token == ".fsm") { - IdString modname = RTLIL::escape_id(next_token(line)); - (void)modname; - IdString signame = RTLIL::escape_id(next_token(line)); - if (encdata.count(signame)) - log_cmd_error("Re-definition of signal '%s' in encfile '%s'!\n", signame, fn); - encdata[signame] = dict(); - ed = &encdata[signame]; - continue; - } - - if (token == ".map") { - Const gold_bits = Const::from_string(next_token(line)); - Const gate_bits = Const::from_string(next_token(line)); - (*ed)[gold_bits] = gate_bits; - continue; - } - - log_cmd_error("Syntax error in encfile '%s'!\n", fn); - } - } - } - - void copy_to_equiv() - { - Module *gold_clone = gold_mod->clone(); - Module *gate_clone = gate_mod->clone(); - - for (auto it : gold_clone->wires().to_vector()) { - if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) - wire_names.insert(it->name); - gold_clone->rename(it, it->name.str() + "_gold"); - } - - for (auto it : gold_clone->cells().to_vector()) { - if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) - cell_names.insert(it->name); - gold_clone->rename(it, it->name.str() + "_gold"); - } - - for (auto it : gate_clone->wires().to_vector()) { - if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) - wire_names.insert(it->name); - gate_clone->rename(it, it->name.str() + "_gate"); - } - - for (auto it : gate_clone->cells().to_vector()) { - if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) - cell_names.insert(it->name); - gate_clone->rename(it, it->name.str() + "_gate"); - } - - gold_clone->cloneInto(equiv_mod); - gate_clone->cloneInto(equiv_mod); - delete gold_clone; - delete gate_clone; - } - - void add_eq_assertion(const SigSpec &gold_sig, const SigSpec &gate_sig) - { - auto eq_wire = equiv_mod->Eqx(NEW_ID, gold_sig, gate_sig); - equiv_mod->addAssert(NEW_ID_SUFFIX("assert"), eq_wire, State::S1); - } - - void find_same_wires() - { - SigMap assign_map(equiv_mod); - SigMap rd_signal_map; - SigPool primary_inputs; - - // list of cells without added $equiv cells - auto cells_list = equiv_mod->cells().to_vector(); - - for (auto id : wire_names) - { - IdString gold_id = id.str() + "_gold"; - IdString gate_id = id.str() + "_gate"; - - Wire *gold_wire = equiv_mod->wire(gold_id); - Wire *gate_wire = equiv_mod->wire(gate_id); - - if (encdata.count(id)) - { - log("Creating encoder/decoder for signal %s.\n", id.unescape()); - - Wire *dec_wire = equiv_mod->addWire(id.str() + "_decoded", gold_wire->width); - Wire *enc_wire = equiv_mod->addWire(id.str() + "_encoded", gate_wire->width); - - SigSpec dec_a, dec_b, dec_s; - SigSpec enc_a, enc_b, enc_s; - - dec_a = SigSpec(State::Sx, dec_wire->width); - enc_a = SigSpec(State::Sx, enc_wire->width); - - for (auto &it : encdata.at(id)) - { - SigSpec dec_sig = gate_wire, dec_pat = it.second; - SigSpec enc_sig = dec_wire, enc_pat = it.first; - - if (GetSize(dec_sig) != GetSize(dec_pat)) - log_error("Invalid pattern %s for signal %s of size %d!\n", - log_signal(dec_pat), log_signal(dec_sig), GetSize(dec_sig)); - - if (GetSize(enc_sig) != GetSize(enc_pat)) - log_error("Invalid pattern %s for signal %s of size %d!\n", - log_signal(enc_pat), log_signal(enc_sig), GetSize(enc_sig)); - - SigSpec reduced_dec_sig, reduced_dec_pat; - for (int i = 0; i < GetSize(dec_sig); i++) - if (dec_pat[i] == State::S0 || dec_pat[i] == State::S1) { - reduced_dec_sig.append(dec_sig[i]); - reduced_dec_pat.append(dec_pat[i]); - } - - SigSpec reduced_enc_sig, reduced_enc_pat; - for (int i = 0; i < GetSize(enc_sig); i++) - if (enc_pat[i] == State::S0 || enc_pat[i] == State::S1) { - reduced_enc_sig.append(enc_sig[i]); - reduced_enc_pat.append(enc_pat[i]); - } - - SigSpec dec_result = it.first; - for (auto &bit : dec_result) - if (bit != State::S1) bit = State::S0; - - SigSpec enc_result = it.second; - for (auto &bit : enc_result) - if (bit != State::S1) bit = State::S0; - - SigSpec dec_eq = equiv_mod->addWire(NEW_ID); - SigSpec enc_eq = equiv_mod->addWire(NEW_ID); - - equiv_mod->addEq(NEW_ID, reduced_dec_sig, reduced_dec_pat, dec_eq); - cells_list.push_back(equiv_mod->addEq(NEW_ID, reduced_enc_sig, reduced_enc_pat, enc_eq)); - - dec_s.append(dec_eq); - enc_s.append(enc_eq); - dec_b.append(dec_result); - enc_b.append(enc_result); - } - - equiv_mod->addPmux(NEW_ID, dec_a, dec_b, dec_s, dec_wire); - equiv_mod->addPmux(NEW_ID, enc_a, enc_b, enc_s, enc_wire); - - rd_signal_map.add(assign_map(gate_wire), enc_wire); - gate_wire = dec_wire; - } - - if (gold_wire == nullptr || gate_wire == nullptr || gold_wire->width != gate_wire->width) { - if (gold_wire && gold_wire->port_id) - log_error("Can't match gold port `%s' to a gate port.\n", gold_wire); - if (gate_wire && gate_wire->port_id) - log_error("Can't match gate port `%s' to a gold port.\n", gate_wire); - continue; - } - - log("Presumably equivalent wires: %s (%s), %s (%s) -> %s\n", - gold_wire, log_signal(assign_map(gold_wire)), - gate_wire, log_signal(assign_map(gate_wire)), id.unescape()); - - if (gold_wire->port_output || gate_wire->port_output) - { - gold_wire->port_input = false; - gate_wire->port_input = false; - gold_wire->port_output = false; - gate_wire->port_output = false; - - Wire *wire = equiv_mod->addWire(id, gold_wire->width); - wire->port_output = true; - - if (make_assert) - { - add_eq_assertion(gold_wire, gate_wire); - equiv_mod->connect(wire, gold_wire); - } - else - { - for (int i = 0; i < wire->width; i++) - equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); - } - - rd_signal_map.add(assign_map(gold_wire), wire); - rd_signal_map.add(assign_map(gate_wire), wire); - } - else - if (gold_wire->port_input || gate_wire->port_input) - { - Wire *wire = equiv_mod->addWire(id, gold_wire->width); - wire->port_input = true; - gold_wire->port_input = false; - gate_wire->port_input = false; - equiv_mod->connect(gold_wire, wire); - equiv_mod->connect(gate_wire, wire); - primary_inputs.add(assign_map(gold_wire)); - primary_inputs.add(assign_map(gate_wire)); - primary_inputs.add(wire); - } - else - { - if (make_assert) - add_eq_assertion(gold_wire, gate_wire); - - else { - Wire *wire = equiv_mod->addWire(id, gold_wire->width); - SigSpec rdmap_gold, rdmap_gate, rdmap_equiv; - - for (int i = 0; i < wire->width; i++) { - if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) { - log(" Skipping signal bit %s [%d]: undriven on gold side.\n", id2cstr(gold_wire->name), i); - continue; - } - if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) { - log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i); - continue; - } - equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); - rdmap_gold.append(SigBit(gold_wire, i)); - rdmap_gate.append(SigBit(gate_wire, i)); - rdmap_equiv.append(SigBit(wire, i)); - } - - rd_signal_map.add(rdmap_gold, rdmap_equiv); - rd_signal_map.add(rdmap_gate, rdmap_equiv); - } - } - } - - for (auto c : cells_list) - for (auto &conn : c->connections()) - if (!ct.cell_output(c->type, conn.first)) { - SigSpec old_sig = assign_map(conn.second); - SigSpec new_sig = rd_signal_map(old_sig); - for (int i = 0; i < GetSize(old_sig); i++) - if (primary_inputs.check(old_sig[i])) - new_sig[i] = old_sig[i]; - if (old_sig != new_sig) { - log("Changing input %s of cell %s (%s): %s -> %s\n", - conn.first.unescape(), c, c->type.unescape(), - log_signal(old_sig), log_signal(new_sig)); - c->setPort(conn.first, new_sig); - } - } - - equiv_mod->fixup_ports(); - } - - void find_same_cells() - { - SigMap assign_map(equiv_mod); - - for (auto id : cell_names) - { - IdString gold_id = id.str() + "_gold"; - IdString gate_id = id.str() + "_gate"; - - Cell *gold_cell = equiv_mod->cell(gold_id); - Cell *gate_cell = equiv_mod->cell(gate_id); - - if (gold_cell == nullptr || gate_cell == nullptr || gold_cell->type != gate_cell->type || !ct.cell_known(gold_cell->type) || - gold_cell->parameters != gate_cell->parameters || GetSize(gold_cell->connections()) != GetSize(gate_cell->connections())) - try_next_cell_name: - continue; - - for (auto gold_conn : gold_cell->connections()) - if (!gate_cell->connections().count(gold_conn.first)) - goto try_next_cell_name; - - log("Presumably equivalent cells: %s %s (%s) -> %s\n", - gold_cell, gate_cell, gold_cell->type.unescape(), id.unescape()); - - for (auto gold_conn : gold_cell->connections()) - { - SigSpec gold_sig = assign_map(gold_conn.second); - SigSpec gate_sig = assign_map(gate_cell->getPort(gold_conn.first)); - - if (ct.cell_output(gold_cell->type, gold_conn.first)) { - equiv_mod->connect(gate_sig, gold_sig); - continue; - } - - if (make_assert) - { - if (gold_sig != gate_sig) - add_eq_assertion(gold_sig, gate_sig); - } - else - { - for (int i = 0; i < GetSize(gold_sig); i++) - if (gold_sig[i] != gate_sig[i]) { - Wire *w = equiv_mod->addWire(NEW_ID); - equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w); - gold_sig[i] = w; - } - } - - gold_cell->setPort(gold_conn.first, gold_sig); - } - - equiv_mod->remove(gate_cell); - equiv_mod->rename(gold_cell, id); - } - } - - void find_undriven_nets(bool mark) - { - undriven_bits.clear(); - assign_map.set(equiv_mod); - - for (auto wire : equiv_mod->wires()) { - for (auto bit : assign_map(wire)) - if (bit.wire) - undriven_bits.insert(bit); - } - - for (auto wire : equiv_mod->wires()) { - if (wire->port_input) - for (auto bit : assign_map(wire)) - undriven_bits.erase(bit); - } - - for (auto cell : equiv_mod->cells()) { - for (auto &conn : cell->connections()) - if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first)) - for (auto bit : assign_map(conn.second)) - undriven_bits.erase(bit); - } - - if (mark) { - SigSpec undriven_sig(undriven_bits); - undriven_sig.sort_and_unify(); - - for (auto chunk : undriven_sig.chunks()) { - log("Setting undriven nets to undef: %s\n", log_signal(chunk)); - equiv_mod->connect(chunk, SigSpec(State::Sx, chunk.width)); - } - } - } - - void run() - { - copy_to_equiv(); - find_undriven_nets(false); - find_same_wires(); - find_same_cells(); - find_undriven_nets(true); - } -}; - -struct EquivMakePass : public Pass { - EquivMakePass() : Pass("equiv_make", "prepare a circuit for equivalence checking") { } - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" equiv_make [options] gold_module gate_module equiv_module\n"); - log("\n"); - log("This creates a module annotated with $equiv cells from two presumably\n"); - log("equivalent modules. Use commands such as 'equiv_simple' and 'equiv_status'\n"); - log("to work with the created equivalent checking module.\n"); - log("\n"); - log(" -inames\n"); - log(" Also match cells and wires with $... names.\n"); - log("\n"); - log(" -blacklist \n"); - log(" Do not match cells or signals that match the names in the file.\n"); - log("\n"); - log(" -encfile \n"); - log(" Match FSM encodings using the description from the file.\n"); - log(" See 'help fsm_recode' for details.\n"); - log("\n"); - log(" -make_assert\n"); - log(" Check equivalence with $assert cells instead of $equiv.\n"); - log(" $eqx (===) is used to compare signals."); - log("\n"); - log("Note: The circuit created by this command is not a miter (with something like\n"); - log("a trigger output), but instead uses $equiv cells to encode the equivalence\n"); - log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n"); - log("\n"); - } - void execute(std::vector args, RTLIL::Design *design) override - { - EquivMakeWorker worker; - worker.ct.setup(design); - worker.inames = false; - worker.make_assert = false; - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - if (args[argidx] == "-inames") { - worker.inames = true; - continue; - } - if (args[argidx] == "-blacklist" && argidx+1 < args.size()) { - worker.blacklists.push_back(args[++argidx]); - continue; - } - if (args[argidx] == "-encfile" && argidx+1 < args.size()) { - worker.encfiles.push_back(args[++argidx]); - continue; - } - if (args[argidx] == "-make_assert") { - worker.make_assert = true; - continue; - } - break; - } - - if (argidx+3 != args.size()) - log_cmd_error("Invalid number of arguments.\n"); - - worker.gold_mod = design->module(RTLIL::escape_id(args[argidx])); - worker.gate_mod = design->module(RTLIL::escape_id(args[argidx+1])); - worker.equiv_mod = design->module(RTLIL::escape_id(args[argidx+2])); - - if (worker.gold_mod == nullptr) - log_cmd_error("Can't find gold module %s.\n", args[argidx]); - - if (worker.gate_mod == nullptr) - log_cmd_error("Can't find gate module %s.\n", args[argidx+1]); - - if (worker.equiv_mod != nullptr) - log_cmd_error("Equiv module %s already exists.\n", args[argidx+2]); - - if (worker.gold_mod->has_memories() || worker.gold_mod->has_processes()) - log_cmd_error("Gold module contains memories or processes. Run 'memory' or 'proc' respectively.\n"); - - if (worker.gate_mod->has_memories() || worker.gate_mod->has_processes()) - log_cmd_error("Gate module contains memories or processes. Run 'memory' or 'proc' respectively.\n"); - - worker.read_blacklists(); - worker.read_encfiles(); - - log_header(design, "Executing EQUIV_MAKE pass (creating equiv checking module).\n"); - - worker.equiv_mod = design->addModule(RTLIL::escape_id(args[argidx+2])); - worker.run(); - } -} EquivMakePass; - -PRIVATE_NAMESPACE_END From c0779f488afdbb2e789ea5ede63a3a7e720fc0e4 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 19 May 2026 14:26:07 +0200 Subject: [PATCH 15/30] Make out of tree build testing possible --- tests/Makefile | 2 +- tests/arch/xilinx/macc.sh | 4 ++-- tests/arch/xilinx/tribuf.sh | 4 ++-- tests/bram/run-single.sh | 2 +- tests/bugpoint/failures.ys | 20 ++++++++++---------- tests/bugpoint/mod_constraints.ys | 20 ++++++++++---------- tests/bugpoint/proc_constraints.ys | 14 +++++++------- tests/bugpoint/raise_error.ys | 14 +++++++------- tests/common.mk | 12 ++++++++++++ tests/functional/test_functional.py | 6 +++--- tests/gen_tests_makefile.py | 4 ++-- tests/liberty/generate_mk.py | 3 +-- tests/memfile/generate_mk.py | 6 +++--- tests/memlib/generate_mk.py | 2 +- tests/rpc/frontend.py | 2 +- tests/rtlil/roundtrip-design.sh | 5 ++--- tests/rtlil/roundtrip-text.sh | 7 +++---- tests/sdc/side-effects.sh | 2 +- tests/sdc/unknown-getter.sh | 2 +- tests/sva/runtest.sh | 8 ++++---- tests/techmap/bug5495.sh | 2 +- tests/techmap/mem_simple_4x1_runtest.sh | 2 +- tests/techmap/recursive_runtest.sh | 2 +- tests/tools/autotest.sh | 11 +++++++---- tests/various/async.sh | 8 ++++---- tests/various/chparam.sh | 8 ++++---- tests/various/clk2fflogic_effects.sh | 4 ++-- tests/various/ezcmdline_plugin.sh | 8 ++++---- tests/various/hierarchy.sh | 6 +++--- tests/various/logger_cmd_error.sh | 2 +- tests/various/logger_fail.sh | 2 +- tests/various/plugin.sh | 10 +++++----- tests/various/sv_implicit_ports.sh | 20 ++++++++++---------- tests/various/svalways.sh | 10 +++++----- tests/verilog/dynamic_range_lhs.sh | 2 +- tests/verilog/local_include.sh | 12 ++++++------ tests/xprop/test.py | 2 +- 37 files changed, 131 insertions(+), 119 deletions(-) diff --git a/tests/Makefile b/tests/Makefile index 794e99c46..05e5410b7 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -100,7 +100,7 @@ makefile-./%: %/Makefile .PHONY: functional functional: ifeq ($(ENABLE_FUNCTIONAL_TESTS),1) - @cd functional && ./run-test.sh + -@cd functional && ./run-test.sh endif vanilla-test: prep makefile-tests functional diff --git a/tests/arch/xilinx/macc.sh b/tests/arch/xilinx/macc.sh index 58b97b646..84798e76b 100644 --- a/tests/arch/xilinx/macc.sh +++ b/tests/arch/xilinx/macc.sh @@ -1,6 +1,6 @@ -../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v +${YOSYS} -qp "synth_xilinx -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v vvp -N ./test_macc -../../../yosys -qp "synth_xilinx -family xc6s -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v +${YOSYS} -qp "synth_xilinx -family xc6s -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v vvp -N ./test_macc diff --git a/tests/arch/xilinx/tribuf.sh b/tests/arch/xilinx/tribuf.sh index eca33e490..354117b74 100644 --- a/tests/arch/xilinx/tribuf.sh +++ b/tests/arch/xilinx/tribuf.sh @@ -1,5 +1,5 @@ -../../../yosys -f verilog -qp "synth_xilinx" ../common/tribuf.v -../../../yosys -f verilog -qp "synth_xilinx -iopad; \ +${YOSYS} -f verilog -qp "synth_xilinx" ../common/tribuf.v +${YOSYS} -f verilog -qp "synth_xilinx -iopad; \ select -assert-count 2 t:IBUF; \ select -assert-count 1 t:INV; \ select -assert-count 1 t:OBUFT" ../common/tribuf.v diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh index 358423f32..f7ce6f644 100644 --- a/tests/bram/run-single.sh +++ b/tests/bram/run-single.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash set -e -../../yosys -qq -f verilog -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ +${YOSYS} -qq -f verilog -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1 -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v diff --git a/tests/bugpoint/failures.ys b/tests/bugpoint/failures.ys index ce8daa8cc..1f7168e33 100644 --- a/tests/bugpoint/failures.ys +++ b/tests/bugpoint/failures.ys @@ -1,29 +1,29 @@ write_file fail.temp << EOF logger -expect error "Missing -script or -command option." 1 -bugpoint -suffix fail -yosys ../../yosys +bugpoint -suffix fail -yosys ${YOSYS} EOF -exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp +exec -expect-return 0 -- ${YOSYS} -qq mods.il -s fail.temp write_file fail.temp << EOF logger -expect error "do not crash on this design" 1 -bugpoint -suffix fail -yosys ../../yosys -command "dump" +bugpoint -suffix fail -yosys ${YOSYS} -command "dump" EOF -exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp +exec -expect-return 0 -- ${YOSYS} -qq mods.il -s fail.temp write_file fail.temp << EOF logger -expect error "returned value 3 instead of expected 7" 1 -bugpoint -suffix fail -yosys ../../yosys -command raise_error -expect-return 7 +bugpoint -suffix fail -yosys ${YOSYS} -command raise_error -expect-return 7 EOF -exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp +exec -expect-return 0 -- ${YOSYS} -qq mods.il -s fail.temp write_file fail.temp << EOF logger -expect error "not found in the log file!" 1 -bugpoint -suffix fail -yosys ../../yosys -command raise_error -grep "nope" +bugpoint -suffix fail -yosys ${YOSYS} -command raise_error -grep "nope" EOF -exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp +exec -expect-return 0 -- ${YOSYS} -qq mods.il -s fail.temp write_file fail.temp << EOF logger -expect error "not found in stderr log!" 1 -bugpoint -suffix fail -yosys ../../yosys -command raise_error -err-grep "nope" +bugpoint -suffix fail -yosys ${YOSYS} -command raise_error -err-grep "nope" EOF -exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp +exec -expect-return 0 -- ${YOSYS} -qq mods.il -s fail.temp diff --git a/tests/bugpoint/mod_constraints.ys b/tests/bugpoint/mod_constraints.ys index f35095510..23b4bf68c 100644 --- a/tests/bugpoint/mod_constraints.ys +++ b/tests/bugpoint/mod_constraints.ys @@ -6,35 +6,35 @@ design -stash base # everything is removed by default design -load base -bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 +bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3 select -assert-count 1 w:* select -assert-mod-count 1 =* select -assert-none c:* # don't remove wires design -load base -bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -modules -cells +bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3 -modules -cells select -assert-count 3 w:* select -assert-mod-count 1 =* select -assert-none c:* # don't remove cells or their connections design -load base -bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -modules +bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3 -wires -modules select -assert-count 5 w:* select -assert-mod-count 1 =* select -assert-count 4 c:* # don't remove cells but do remove their connections design -load base -bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -modules -connections +bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3 -wires -modules -connections select -assert-count 1 w:* select -assert-mod-count 1 =* select -assert-count 4 c:* # don't remove modules design -load base -bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -cells +bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3 -wires -cells select -assert-count 1 w:* select -assert-mod-count 3 =* select -assert-none c:* @@ -42,7 +42,7 @@ select -assert-none c:* # can keep wires design -load base setattr -set bugpoint_keep 1 w:w_b -bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 +bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3 select -assert-count 2 w:* select -assert-mod-count 1 =* select -assert-none c:* @@ -50,7 +50,7 @@ select -assert-none c:* # a wire with keep won't keep the cell/module containing it design -load base setattr -set bugpoint_keep 1 w:w_o -bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 +bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3 select -assert-count 1 w:* select -assert-mod-count 1 =* select -assert-none c:* @@ -58,7 +58,7 @@ select -assert-none c:* # can keep cells (and do it without the associated module) design -load base setattr -set bugpoint_keep 1 c:c_a -bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 +bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3 select -assert-count 1 w:* select -assert-mod-count 1 =* select -assert-count 1 c:* @@ -66,7 +66,7 @@ select -assert-count 1 c:* # can keep modules design -load base setattr -mod -set bugpoint_keep 1 m_a -bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 +bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3 select -assert-count 1 w:* select -assert-mod-count 2 =* select -assert-none c:* @@ -77,7 +77,7 @@ write_file script.temp << EOF select -assert-none w:w_a %co* w:w_c %ci* %i EOF design -load base -bugpoint -suffix mods -yosys ../../yosys -script script.temp -grep "Assertion failed" +bugpoint -suffix mods -yosys ${YOSYS} -script script.temp -grep "Assertion failed" select -assert-count 5 w:* select -assert-mod-count 2 =* select -assert-count 2 c:* diff --git a/tests/bugpoint/proc_constraints.ys b/tests/bugpoint/proc_constraints.ys index 22b8b3c60..6c905b48c 100644 --- a/tests/bugpoint/proc_constraints.ys +++ b/tests/bugpoint/proc_constraints.ys @@ -4,18 +4,18 @@ design -stash err_q # processes get removed by default design -load err_q -bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 +bugpoint -suffix procs -yosys ${YOSYS} -command raise_error -expect-return 4 select -assert-none p:* # individual processes can be kept design -load err_q setattr -set bugpoint_keep 1 p:proc_a -bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 +bugpoint -suffix procs -yosys ${YOSYS} -command raise_error -expect-return 4 select -assert-count 1 p:* # all processes can be kept design -load err_q -bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -wires +bugpoint -suffix procs -yosys ${YOSYS} -command raise_error -expect-return 4 -wires select -assert-count 2 p:* # d and clock are connected after proc @@ -26,24 +26,24 @@ select -assert-count 3 w:clock %co # no assigns means no d design -load err_q -bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -assigns +bugpoint -suffix procs -yosys ${YOSYS} -command raise_error -expect-return 4 -assigns proc select -assert-count 1 w:d %co # no updates means no clock design -load err_q -bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -updates +bugpoint -suffix procs -yosys ${YOSYS} -command raise_error -expect-return 4 -updates proc select -assert-count 1 w:clock %co # can remove ports design -load err_q select -assert-count 5 x:* -bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -ports +bugpoint -suffix procs -yosys ${YOSYS} -command raise_error -expect-return 4 -ports select -assert-none x:* # can keep ports design -load err_q setattr -set bugpoint_keep 1 i:d o:q -bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -ports +bugpoint -suffix procs -yosys ${YOSYS} -command raise_error -expect-return 4 -ports select -assert-count 2 x:* diff --git a/tests/bugpoint/raise_error.ys b/tests/bugpoint/raise_error.ys index 79127deff..3985c7115 100644 --- a/tests/bugpoint/raise_error.ys +++ b/tests/bugpoint/raise_error.ys @@ -24,21 +24,21 @@ logger -check-expected design -load read setattr -mod -unset raise_error def other dump -bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 7 +bugpoint -suffix error -yosys ${YOSYS} -command raise_error -expect-return 7 select -assert-mod-count 1 =* select -assert-mod-count 1 top # raise_error -always still uses 'raise_error' attribute if possible design -load read setattr -mod -unset raise_error def other -bugpoint -suffix error -yosys ../../yosys -command "raise_error -always" -expect-return 7 +bugpoint -suffix error -yosys ${YOSYS} -command "raise_error -always" -expect-return 7 select -assert-mod-count 1 =* select -assert-mod-count 1 top # raise_error with string prints message and exits with 1 design -load read setattr -mod -unset raise_error top def -bugpoint -suffix error -yosys ../../yosys -command raise_error -grep "help me" -expect-return 1 +bugpoint -suffix error -yosys ${YOSYS} -command raise_error -grep "help me" -expect-return 1 select -assert-mod-count 1 =* select -assert-mod-count 1 other @@ -46,18 +46,18 @@ select -assert-mod-count 1 other design -load read setattr -mod -unset raise_error top delete other -bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 1 +bugpoint -suffix error -yosys ${YOSYS} -command raise_error -expect-return 1 select -assert-mod-count 1 =* select -assert-mod-count 1 def # raise_error -stderr prints to stderr and exits with 1 design -load read setattr -mod -unset raise_error top def -bugpoint -suffix error -yosys ../../yosys -command "raise_error -stderr" -err-grep "help me" -expect-return 1 +bugpoint -suffix error -yosys ${YOSYS} -command "raise_error -stderr" -err-grep "help me" -expect-return 1 select -assert-mod-count 1 =* select -assert-mod-count 1 other # empty design can raise_error -always design -reset -bugpoint -suffix error -yosys ../../yosys -command "raise_error -always" -grep "ERROR: No 'raise_error' attribute found" -expect-return 1 -bugpoint -suffix error -yosys ../../yosys -command "raise_error -always -stderr" -err-grep "No 'raise_error' attribute found" -expect-return 1 +bugpoint -suffix error -yosys ${YOSYS} -command "raise_error -always" -grep "ERROR: No 'raise_error' attribute found" -expect-return 1 +bugpoint -suffix error -yosys ${YOSYS} -command "raise_error -always -stderr" -err-grep "No 'raise_error' attribute found" -expect-return 1 diff --git a/tests/common.mk b/tests/common.mk index 044054e0c..59ea599c0 100644 --- a/tests/common.mk +++ b/tests/common.mk @@ -1,3 +1,15 @@ +ROOT_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +BUILD_DIR ?= $(ROOT_DIR)/.. + +YOSYS ?= $(BUILD_DIR)/yosys +ABC ?= $(BUILD_DIR)/yosys-abc +YOSYS_FILTERLIB ?= $(BUILD_DIR)/yosys-filterlib +YOSYS_CONFIG ?= $(BUILD_DIR)/yosys-config + +export YOSYS +export YOSYS_CONFIG +export ABC + all: ifndef OVERRIDE_MAIN diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index 661af14d1..9df832864 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -1,6 +1,6 @@ import subprocess import pytest -import sys +import os import shlex from pathlib import Path @@ -18,7 +18,7 @@ def run(cmd, **kwargs): assert status.returncode == 0, f"{cmd[0]} failed" def yosys(script): - run([base_path / 'yosys', '-Q', '-p', script]) + run([os.environ.get("YOSYS", "../../yosys"), '-Q', '-p', script]) def compile_cpp(in_path, out_path, args): run(['g++', '-g', '-std=c++20'] + args + [str(in_path), '-o', str(out_path)]) @@ -35,7 +35,7 @@ def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""): # since yosys sim aborts on simulation mismatch to generate vcd output # we have to re-run with a different set of flags # on this run we ignore output and return code, we just want a best-effort attempt to get a vcd - subprocess.run([base_path / 'yosys', '-Q', '-p', + subprocess.run([os.environ.get("YOSYS", "../../yosys"), '-Q', '-p', f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_out_file)} -a -r {quote(vcd_reference_file)} -scope gold -timescale 1us -fst-noinit'], capture_output=True, check=False) raise diff --git a/tests/gen_tests_makefile.py b/tests/gen_tests_makefile.py index e4e44241c..77602a9a0 100644 --- a/tests/gen_tests_makefile.py +++ b/tests/gen_tests_makefile.py @@ -97,7 +97,7 @@ def print_header(extra=None): print(f"ifneq ($(wildcard {yosys_basedir}/Makefile.conf),)") print(f"include {yosys_basedir}/Makefile.conf") print(f"endif") - print(f"YOSYS ?= {yosys_basedir}/yosys") + print("") print("export YOSYS_MAX_THREADS := 4") if extra: @@ -128,7 +128,7 @@ def generate_custom(callback, extra=None): callback() def generate_autotest_file(test_file, commands): - cmd = f"../tools/autotest.sh -G -j ${{SEEDOPT}} ${{EXTRA_FLAGS}} {test_file}; \\\n{commands}" + cmd = f"../tools/autotest.sh -G -j ${{SEEDOPT}} -Y ${{YOSYS}} ${{EXTRA_FLAGS}} {test_file}; \\\n{commands}" generate_target(test_file, cmd) def generate_autotest(pattern, extra_flags, cmds=""): diff --git a/tests/liberty/generate_mk.py b/tests/liberty/generate_mk.py index b2559cced..45a26caa9 100644 --- a/tests/liberty/generate_mk.py +++ b/tests/liberty/generate_mk.py @@ -36,8 +36,7 @@ def main(): lib_tests() ys_tests() - gen_tests_makefile.generate_custom(callback, - [f"YOSYS_FILTERLIB ?= {gen_tests_makefile.yosys_basedir}/yosys-filterlib"]) + gen_tests_makefile.generate_custom(callback) if __name__ == "__main__": diff --git a/tests/memfile/generate_mk.py b/tests/memfile/generate_mk.py index e6351bc51..a43257d35 100644 --- a/tests/memfile/generate_mk.py +++ b/tests/memfile/generate_mk.py @@ -40,19 +40,19 @@ def create_tests(): gen_tests_makefile.generate_cmd_test("child_content1", [ f"{setup}", - 'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v; ' + 'cd temp && $(YOSYS) -qp "read_verilog -defer ../memory.v; ' 'chparam -set MEMFILE \\"content1.dat\\" memory"' ]) gen_tests_makefile.generate_cmd_test("child_content2_temp", [ f"{setup}", - 'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v; ' + 'cd temp && $(YOSYS) -qp "read_verilog -defer ../memory.v; ' 'chparam -set MEMFILE \\"temp/content2.dat\\" memory"' ]) gen_tests_makefile.generate_cmd_test("child_content2_direct", [ f"{setup}", - 'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v; ' + 'cd temp && $(YOSYS) -qp "read_verilog -defer ../memory.v; ' 'chparam -set MEMFILE \\"temp/content2.dat\\" memory"' ]) diff --git a/tests/memlib/generate_mk.py b/tests/memlib/generate_mk.py index 5f846a573..13b62b1d8 100644 --- a/tests/memlib/generate_mk.py +++ b/tests/memlib/generate_mk.py @@ -1574,7 +1574,7 @@ def create_tests(): for lib in t.libs: libs_args += f" -l memlib_{lib}.v" cmd = ( - f"../tools/autotest.sh -G -j ${{SEEDOPT}} ${{EXTRA_FLAGS}} " + f"../tools/autotest.sh -G -j ${{SEEDOPT}} -Y ${{YOSYS}} " f"-p 'script ../t_{t.name}.ys'" f"{libs_args} " f"t_{t.name}.v || (cat t_{t.name}.err; exit 1)" diff --git a/tests/rpc/frontend.py b/tests/rpc/frontend.py index 2729cd472..6619fb153 100644 --- a/tests/rpc/frontend.py +++ b/tests/rpc/frontend.py @@ -87,7 +87,7 @@ def main(): sock.bind(args.path) try: sock.listen(1) - ys_proc = subprocess.Popen(["../../yosys", "-ql", "unix.log", "-p", "connect_rpc -path {}; read_verilog design.v; hierarchy -top top; flatten; select -assert-count 1 t:$neg".format(args.path)]) + ys_proc = subprocess.Popen([os.environ.get("YOSYS", "../../yosys"), "-ql", "unix.log", "-p", "connect_rpc -path {}; read_verilog design.v; hierarchy -top top; flatten; select -assert-count 1 t:$neg".format(args.path)]) conn, addr = sock.accept() file = conn.makefile("rw") while True: diff --git a/tests/rtlil/roundtrip-design.sh b/tests/rtlil/roundtrip-design.sh index 018e363c7..5d6f62c41 100644 --- a/tests/rtlil/roundtrip-design.sh +++ b/tests/rtlil/roundtrip-design.sh @@ -1,10 +1,9 @@ set -euo pipefail -YS=../../yosys mkdir -p temp -$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-push.il; design -push; design -pop; write_rtlil temp/roundtrip-design-pop.il" +${YOSYS} -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-push.il; design -push; design -pop; write_rtlil temp/roundtrip-design-pop.il" diff temp/roundtrip-design-push.il temp/roundtrip-design-pop.il -$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-save.il; design -save foo; design -load foo; write_rtlil temp/roundtrip-design-load.il" +${YOSYS} -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-save.il; design -save foo; design -load foo; write_rtlil temp/roundtrip-design-load.il" diff temp/roundtrip-design-save.il temp/roundtrip-design-load.il diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh index 35417cff7..7d562723b 100644 --- a/tests/rtlil/roundtrip-text.sh +++ b/tests/rtlil/roundtrip-text.sh @@ -1,5 +1,4 @@ set -euo pipefail -YS=../../yosys mkdir -p temp @@ -11,7 +10,7 @@ remove_empty_lines() { } # write_rtlil and dump are equivalent -$YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.write.il" +${YOSYS} -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.write.il" remove_empty_lines temp/roundtrip-text.dump.il remove_empty_lines temp/roundtrip-text.write.il # Trim first line ("Generated by Yosys ...") @@ -19,13 +18,13 @@ tail -n +2 temp/roundtrip-text.write.il > temp/roundtrip-text.write-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.write-nogen.il # Loading and writing it out again doesn't change the RTLIL -$YS -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il" +${YOSYS} -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il" remove_empty_lines temp/roundtrip-text.reload.il tail -n +2 temp/roundtrip-text.reload.il > temp/roundtrip-text.reload-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-nogen.il # Hashing differences don't change the RTLIL -$YS --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload-hash.il" +${YOSYS} --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload-hash.il" remove_empty_lines temp/roundtrip-text.reload-hash.il tail -n +2 temp/roundtrip-text.reload-hash.il > temp/roundtrip-text.reload-hash-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il diff --git a/tests/sdc/side-effects.sh b/tests/sdc/side-effects.sh index 88d6154a1..23b1a601e 100755 --- a/tests/sdc/side-effects.sh +++ b/tests/sdc/side-effects.sh @@ -1,4 +1,4 @@ #!/usr/bin/env bash -../../yosys -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc side-effects.sdc' | grep 'This should print something: +${YOSYS} -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc side-effects.sdc' | grep 'This should print something: YOSYS_SDC_MAGIC_NODE_0' diff --git a/tests/sdc/unknown-getter.sh b/tests/sdc/unknown-getter.sh index 9038834c6..acf5f5cf1 100755 --- a/tests/sdc/unknown-getter.sh +++ b/tests/sdc/unknown-getter.sh @@ -2,4 +2,4 @@ set -euo pipefail -! ../../yosys -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc get_foo.sdc' 2>&1 | grep 'Unknown getter' +! ${YOSYS} -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc get_foo.sdc' 2>&1 | grep 'Unknown getter' diff --git a/tests/sva/runtest.sh b/tests/sva/runtest.sh index 7692a5f9a..db6c37011 100644 --- a/tests/sva/runtest.sh +++ b/tests/sva/runtest.sh @@ -59,7 +59,7 @@ generate_sby() { if [ -f $prefix.ys ]; then set -x - $PWD/../../yosys -q -e "Assert .* failed." -s $prefix.ys + ${YOSYS} -q -e "Assert .* failed." -s $prefix.ys elif [ -f $prefix.sv ]; then generate_sby pass > ${prefix}_pass.sby generate_sby fail > ${prefix}_fail.sby @@ -67,8 +67,8 @@ elif [ -f $prefix.sv ]; then # Check that SBY is up to date enough for this yosys version if sby --help | grep -q -e '--status'; then set -x - sby --yosys $PWD/../../yosys -f ${prefix}_pass.sby - sby --yosys $PWD/../../yosys -f ${prefix}_fail.sby + sby --yosys ${YOSYS} -f ${prefix}_pass.sby + sby --yosys ${YOSYS} -f ${prefix}_fail.sby else echo "sva test '${prefix}' requires an up to date SBY, skipping" fi @@ -78,7 +78,7 @@ else # Check that SBY is up to date enough for this yosys version if sby --help | grep -q -e '--status'; then set -x - sby --yosys $PWD/../../yosys -f ${prefix}.sby + sby --yosys ${YOSYS} -f ${prefix}.sby else echo "sva test '${prefix}' requires an up to date SBY, skipping" fi diff --git a/tests/techmap/bug5495.sh b/tests/techmap/bug5495.sh index 476727755..d1ade0fb2 100755 --- a/tests/techmap/bug5495.sh +++ b/tests/techmap/bug5495.sh @@ -5,7 +5,7 @@ if ! which timeout ; then exit 0 fi -if ! timeout 10 ../../yosys bug5495.v -p 'hierarchy; techmap; abc -script bug5495.abc' ; then +if ! timeout 10 ${YOSYS} bug5495.v -p 'hierarchy; techmap; abc -script bug5495.abc' ; then echo "Yosys failed to complete" exit 1 fi diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh index d7738aafb..4d8494a6e 100644 --- a/tests/techmap/mem_simple_4x1_runtest.sh +++ b/tests/techmap/mem_simple_4x1_runtest.sh @@ -1,3 +1,3 @@ #!/usr/bin/env bash -exec ../tools/autotest.sh -G -j $@ -p 'proc; opt; memory -nomap; techmap -map ../mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v +exec ../tools/autotest.sh -G -Y ${YOSYS} -j $@ -p 'proc; opt; memory -nomap; techmap -map ../mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v diff --git a/tests/techmap/recursive_runtest.sh b/tests/techmap/recursive_runtest.sh index 564d678fa..541e323f7 100644 --- a/tests/techmap/recursive_runtest.sh +++ b/tests/techmap/recursive_runtest.sh @@ -1,3 +1,3 @@ set -e -../../yosys -p 'read_verilog recursive.v; hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' +${YOSYS} -p 'read_verilog recursive.v; hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 0fd80cdaf..47c199cf7 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -24,6 +24,7 @@ warn_iverilog_git=false firrtl2verilog="" xfirrtl="../xfirrtl" abcprog="$toolsdir/../../yosys-abc" +yosysprog="$toolsdir/../../yosys" exec {lock}<"$toolsdir"; flock "$lock" 1>&2 if [ ! -f "$toolsdir/cmp_tbdata" -o "$toolsdir/cmp_tbdata.c" -nt "$toolsdir/cmp_tbdata" ]; then @@ -31,7 +32,7 @@ if [ ! -f "$toolsdir/cmp_tbdata" -o "$toolsdir/cmp_tbdata.c" -nt "$toolsdir/cmp_ fi flock -u "$lock"; exec {lock}>&- -while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do +while getopts xmGl:wkjvref:s:p:n:S:I:A:Y:-: opt; do case "$opt" in x) use_xsim=true ;; @@ -70,6 +71,8 @@ while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do minclude_opts="$minclude_opts +incdir+$OPTARG" ;; A) abcprog="$OPTARG" ;; + Y) + yosysprog="$OPTARG" ;; -) case "${OPTARG}" in xfirrtl) @@ -159,7 +162,7 @@ do fi if [ ! -f ../${bn}_tb.v ]; then - "$toolsdir"/../../yosys -f "$frontend $include_opts -D_AUTOTB" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext} + $yosysprog -f "$frontend $include_opts -D_AUTOTB" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext} else cp ../${bn}_tb.v ${bn}_tb.v fi @@ -173,7 +176,7 @@ do test_count=0 test_passes() { - "$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@" + $yosysprog -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@" touch ${bn}.iverilog compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \ ${bn}_tb.v ${bn}_syn${test_count}.v "${libs[@]}" \ @@ -203,7 +206,7 @@ do test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${refext} if [ -n "$firrtl2verilog" ]; then if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then - "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext} + $yosysprog -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext} $firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine" ${bn}_ref.fir.v fi diff --git a/tests/various/async.sh b/tests/various/async.sh index 9d956c1cd..df56f6427 100644 --- a/tests/various/async.sh +++ b/tests/various/async.sh @@ -1,9 +1,9 @@ #!/usr/bin/env bash set -ex -../../yosys -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v -../../yosys -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v -../../yosys -q -o async_a2s.v -r uut -p 'prep; async2sync; rename uut a2s' async.v -../../yosys -q -o async_ffl.v -r uut -p 'prep; clk2fflogic; rename uut ffl' async.v +${YOSYS} -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v +${YOSYS} -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v +${YOSYS} -q -o async_a2s.v -r uut -p 'prep; async2sync; rename uut a2s' async.v +${YOSYS} -q -o async_ffl.v -r uut -p 'prep; clk2fflogic; rename uut ffl' async.v iverilog -o async_sim -DTESTBENCH async.v async_???.v vvp -N async_sim > async.out tail async.out diff --git a/tests/various/chparam.sh b/tests/various/chparam.sh index 0c237112e..d793dfc5b 100644 --- a/tests/various/chparam.sh +++ b/tests/various/chparam.sh @@ -35,18 +35,18 @@ module top #( endmodule EOT -if ../../yosys -q -p 'verific -sv chparam1.sv'; then - ../../yosys -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ +if ${YOSYS} -q -p 'verific -sv chparam1.sv'; then + ${YOSYS} -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ -p 'async2sync' \ -p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \ -p 'sat -falsify -prove-asserts -show-ports -set din[0] 0' - ../../yosys -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ + ${YOSYS} -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ -p 'async2sync' \ -p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \ -p 'sat -falsify -prove-asserts -show-ports -set din[0] 0' fi -../../yosys -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ +${YOSYS} -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ -p 'async2sync' \ -p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \ -p 'sat -falsify -prove-asserts -show-ports -set din[0] 0' diff --git a/tests/various/clk2fflogic_effects.sh b/tests/various/clk2fflogic_effects.sh index 0d133ffdd..6d0046161 100755 --- a/tests/various/clk2fflogic_effects.sh +++ b/tests/various/clk2fflogic_effects.sh @@ -3,14 +3,14 @@ set -e # TODO: when sim gets native $check support, remove the -DNO_ASSERT here echo Running yosys sim -../../yosys -q -p " +${YOSYS} -q -p " read_verilog -formal -DNO_ASSERT clk2fflogic_effects.sv hierarchy -top top; proc;; tee -q -o clk2fflogic_effects.sim.log sim -q -n 32 " echo Running yosys clk2fflogic sim -../../yosys -q -p " +${YOSYS} -q -p " read_verilog -formal clk2fflogic_effects.sv hierarchy -top top; proc;; clk2fflogic;; diff --git a/tests/various/ezcmdline_plugin.sh b/tests/various/ezcmdline_plugin.sh index cad0475a8..91579d7cb 100644 --- a/tests/various/ezcmdline_plugin.sh +++ b/tests/various/ezcmdline_plugin.sh @@ -4,9 +4,9 @@ DIR=$(cd "$(dirname "$0")" && pwd) BASEDIR=$(cd "$DIR/../.." && pwd) rm -f "$DIR/ezcmdline_plugin.so" chmod +x "$DIR/ezcmdline_dummy_solver" -CXXFLAGS=$("$BASEDIR/yosys-config" --cxxflags) -DATDIR=$("$BASEDIR/yosys-config" --datdir) +CXXFLAGS=$(${YOSYS_CONFIG} --cxxflags) +DATDIR=$(${YOSYS_CONFIG} --datdir) DATDIR=${DATDIR//\//\\\/} CXXFLAGS=${CXXFLAGS//$DATDIR/..\/..\/share} -"$BASEDIR/yosys-config" --exec --cxx ${CXXFLAGS} -I"$BASEDIR" --ldflags -shared -o "$DIR/ezcmdline_plugin.so" "$DIR/ezcmdline_plugin.cc" -"$BASEDIR/yosys" -m "$DIR/ezcmdline_plugin.so" -p "ezcmdline_test -cmd $DIR/ezcmdline_dummy_solver" | grep -q "ezcmdline_test passed!" +${YOSYS_CONFIG} --exec --cxx ${CXXFLAGS} -I"$BASEDIR" --ldflags -shared -o "$DIR/ezcmdline_plugin.so" "$DIR/ezcmdline_plugin.cc" +${YOSYS} -m "$DIR/ezcmdline_plugin.so" -p "ezcmdline_test -cmd $DIR/ezcmdline_dummy_solver" | grep -q "ezcmdline_test passed!" diff --git a/tests/various/hierarchy.sh b/tests/various/hierarchy.sh index 9dbd1c89f..637f4be87 100644 --- a/tests/various/hierarchy.sh +++ b/tests/various/hierarchy.sh @@ -4,7 +4,7 @@ set -e echo -n " TOP first - " -../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module" +${YOSYS} -s - <<- EOY | grep "Automatically selected TOP as design top module" read_verilog << EOV module TOP(a, y); input a; @@ -23,7 +23,7 @@ echo -n " TOP first - " EOY echo -n " TOP last - " -../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module" +${YOSYS} -s - <<- EOY | grep "Automatically selected TOP as design top module" read_verilog << EOV module aoi12(a, y); input a; @@ -42,7 +42,7 @@ echo -n " TOP last - " EOY echo -n " no explicit top - " -../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module." +${YOSYS} -s - <<- EOY | grep "Automatically selected noTop as design top module." read_verilog << EOV module aoi12(a, y); input a; diff --git a/tests/various/logger_cmd_error.sh b/tests/various/logger_cmd_error.sh index dd0585965..1a1ca474c 100755 --- a/tests/various/logger_cmd_error.sh +++ b/tests/various/logger_cmd_error.sh @@ -2,7 +2,7 @@ trap 'echo "ERROR in logger_cmd_error.sh" >&2; exit 1' ERR -(../../yosys -v 3 -C <&1` + output=`${YOSYS} -q "$@" 2>&1` if [ $? -ne 1 ]; then fail "exit code for '$desc' was not 1" fi diff --git a/tests/various/plugin.sh b/tests/various/plugin.sh index 75b4c9e56..4e645ee17 100644 --- a/tests/various/plugin.sh +++ b/tests/various/plugin.sh @@ -1,12 +1,12 @@ set -e rm -f plugin.so rm -rf plugin_search -CXXFLAGS=$(../../yosys-config --cxxflags) -DATDIR=$(../../yosys-config --datdir) +CXXFLAGS=$(${YOSYS_CONFIG} --cxxflags) +DATDIR=$(${YOSYS_CONFIG} --datdir) DATDIR=${DATDIR//\//\\\/} CXXFLAGS=${CXXFLAGS//$DATDIR/..\/..\/share} -../../yosys-config --exec --cxx ${CXXFLAGS} --ldflags -shared -o plugin.so plugin.cc -../../yosys -m ./plugin.so -p "test" | grep -q "Plugin test passed!" +${YOSYS_CONFIG} --exec --cxx ${CXXFLAGS} --ldflags -shared -o plugin.so plugin.cc +${YOSYS} -m ./plugin.so -p "test" | grep -q "Plugin test passed!" mkdir -p plugin_search mv plugin.so plugin_search/plugin.so -YOSYS_PLUGIN_PATH=$PWD/plugin_search ../../yosys -m plugin.so -p "test" | grep -q "Plugin test passed!" +YOSYS_PLUGIN_PATH=$PWD/plugin_search ${YOSYS} -m plugin.so -p "test" | grep -q "Plugin test passed!" diff --git a/tests/various/sv_implicit_ports.sh b/tests/various/sv_implicit_ports.sh index 5266fffe5..ace95b3ba 100755 --- a/tests/various/sv_implicit_ports.sh +++ b/tests/various/sv_implicit_ports.sh @@ -3,7 +3,7 @@ trap 'echo "ERROR in sv_implicit_ports.sh" >&2; exit 1' ERR # Simple case -../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <&1 | grep -F "ERROR: No matching wire for implicit port connection \`b' of cell top.add_i (add)." > /dev/null # Incorrectly sized wire -((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <&1 | grep -F "ERROR: Width mismatch between wire (7 bits) and port (8 bits) for implicit port connection \`b' of cell top.add_i (add)." > /dev/null # Defaults -../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <&1 | grep -F "ERROR: Width mismatch between wire (8 bits) and port (6 bits) for implicit port connection \`q' of cell top.add_i (add)." > /dev/null # Mixed implicit and explicit 1 -../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <&2; exit 1' ERR # Good case -../../yosys -f "verilog -sv" -qp proc - <&1 | grep -F ":3: ERROR: syntax error, unexpected '@'" > /dev/null # Incorrect use of always_comb -((../../yosys -f "verilog -sv" -qp proc -|| true) <&1 | grep -F "ERROR: Latch inferred for signal \`\\top.\\q' from always_comb process" > /dev/null # Incorrect use of always_latch -((../../yosys -f "verilog -sv" -qp proc -|| true) <&1 | grep -F "ERROR: No latch inferred for signal \`\\top.\\q' from always_latch process" > /dev/null # Incorrect use of always_ff -((../../yosys -f "verilog -sv" -qp proc -|| true) < $include -$yosys $test $source +$yosyscmd $test $source # include local to cwd mkdir -p $subdir cp $source $subdir -$yosys $test $subdir/$source +$yosyscmd $test $subdir/$source # include local to source mv $include $subdir -$yosys $test $subdir/$source +$yosyscmd $test $subdir/$source # include local to source, and source is given as an absolute path -$yosys $test $(pwd)/$subdir/$source +$yosyscmd $test $(pwd)/$subdir/$source diff --git a/tests/xprop/test.py b/tests/xprop/test.py index e2cddf679..94c52aecc 100644 --- a/tests/xprop/test.py +++ b/tests/xprop/test.py @@ -47,7 +47,7 @@ if "clean" in steps: def yosys(command): - subprocess.check_call(["../../../yosys", "-Qp", command]) + subprocess.check_call([os.environ.get("YOSYS", "../../yosys"), "-Qp", command]) def remove(file): try: From 15e09163cdc3d45c9c80933dbf7bff21d5737f96 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 19 May 2026 14:29:06 +0200 Subject: [PATCH 16/30] Do not use Makefile.conf --- tests/aiger/generate_mk.py | 5 ----- tests/common.mk | 2 ++ tests/gen_tests_makefile.py | 6 ------ 3 files changed, 2 insertions(+), 11 deletions(-) diff --git a/tests/aiger/generate_mk.py b/tests/aiger/generate_mk.py index e6f3f4091..47e94884a 100644 --- a/tests/aiger/generate_mk.py +++ b/tests/aiger/generate_mk.py @@ -55,11 +55,6 @@ def create_tests(): ])) extra = [ - "ifneq ($(ABCEXTERNAL),)", - "ABC ?= $(ABCEXTERNAL)", - "else", - f"ABC ?= {gen_tests_makefile.yosys_basedir}/yosys-abc", - "endif", "SHELL := /usr/bin/env bash", ] diff --git a/tests/common.mk b/tests/common.mk index 59ea599c0..1636a880b 100644 --- a/tests/common.mk +++ b/tests/common.mk @@ -5,10 +5,12 @@ YOSYS ?= $(BUILD_DIR)/yosys ABC ?= $(BUILD_DIR)/yosys-abc YOSYS_FILTERLIB ?= $(BUILD_DIR)/yosys-filterlib YOSYS_CONFIG ?= $(BUILD_DIR)/yosys-config +YOSYS_MAX_THREADS ?= 4 export YOSYS export YOSYS_CONFIG export ABC +export YOSYS_MAX_THREADS all: diff --git a/tests/gen_tests_makefile.py b/tests/gen_tests_makefile.py index 77602a9a0..034883a2c 100644 --- a/tests/gen_tests_makefile.py +++ b/tests/gen_tests_makefile.py @@ -94,12 +94,6 @@ def generate_tests(argv, cmds): def print_header(extra=None): print(f"include {common_mk}") - print(f"ifneq ($(wildcard {yosys_basedir}/Makefile.conf),)") - print(f"include {yosys_basedir}/Makefile.conf") - print(f"endif") - - print("") - print("export YOSYS_MAX_THREADS := 4") if extra: for line in extra: print(line) From 2b3f4c37f5bebc06e56fb8be74b96e31f13a0d99 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 19 May 2026 14:42:08 +0200 Subject: [PATCH 17/30] Fix functional tests --- tests/common.mk | 2 ++ tests/functional/test_smtbmc_witness_mismatch.py | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/tests/common.mk b/tests/common.mk index 1636a880b..1d70c20a9 100644 --- a/tests/common.mk +++ b/tests/common.mk @@ -5,10 +5,12 @@ YOSYS ?= $(BUILD_DIR)/yosys ABC ?= $(BUILD_DIR)/yosys-abc YOSYS_FILTERLIB ?= $(BUILD_DIR)/yosys-filterlib YOSYS_CONFIG ?= $(BUILD_DIR)/yosys-config +YOSYS_SMTBMC ?= $(BUILD_DIR)/yosys-smtbmc YOSYS_MAX_THREADS ?= 4 export YOSYS export YOSYS_CONFIG +export YOSYS_SMTBMC export ABC export YOSYS_MAX_THREADS diff --git a/tests/functional/test_smtbmc_witness_mismatch.py b/tests/functional/test_smtbmc_witness_mismatch.py index f13620f1d..60cd87073 100644 --- a/tests/functional/test_smtbmc_witness_mismatch.py +++ b/tests/functional/test_smtbmc_witness_mismatch.py @@ -1,3 +1,4 @@ +import os import json import shutil import subprocess @@ -21,7 +22,7 @@ def write_smt2(tmp_path, verilog_text): vfile = tmp_path / "design.v" smt2 = tmp_path / "design.smt2" vfile.write_text(verilog_text) - run([base_path / "yosys", "-Q", "-p", + run([os.environ.get("YOSYS", "../../yosys"), "-Q", "-p", f"read_verilog {vfile}; prep -top top; write_smt2 {smt2}"]) return smt2 @@ -61,7 +62,7 @@ def write_yw(yw_path, signals, bits): def run_smtbmc(smt2_path, yw_path): """Run yosys-smtbmc on the SMT2 file with a witness trace.""" cmd = [ - base_path / "yosys-smtbmc", + os.environ.get("YOSYS_SMTBMC", "../../yosys-smtbmc"), "-s", "z3", "-m", "top", "--check-witness", From 07924a3c6219374cdb58db01230f1e7636cc72a2 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 19 May 2026 15:15:41 +0200 Subject: [PATCH 18/30] Use common.mk for sva tests as well --- tests/sva/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/sva/Makefile b/tests/sva/Makefile index dcabcf42b..d8c206664 100644 --- a/tests/sva/Makefile +++ b/tests/sva/Makefile @@ -1,3 +1,5 @@ +OVERRIDE_MAIN=1 +include ../common.mk TESTS = $(sort $(basename $(wildcard *.sv)) $(basename $(wildcard *.vhd))) From 4c8e61a52bccc8b889b7390d705df47302afbd1e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 19 May 2026 16:08:21 +0200 Subject: [PATCH 19/30] Expose SBY binary location --- tests/common.mk | 2 ++ tests/sva/runtest.sh | 10 +++++----- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/tests/common.mk b/tests/common.mk index 1d70c20a9..ef6982514 100644 --- a/tests/common.mk +++ b/tests/common.mk @@ -1,6 +1,7 @@ ROOT_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) BUILD_DIR ?= $(ROOT_DIR)/.. +SBY ?= sby YOSYS ?= $(BUILD_DIR)/yosys ABC ?= $(BUILD_DIR)/yosys-abc YOSYS_FILTERLIB ?= $(BUILD_DIR)/yosys-filterlib @@ -12,6 +13,7 @@ export YOSYS export YOSYS_CONFIG export YOSYS_SMTBMC export ABC +export SBY export YOSYS_MAX_THREADS all: diff --git a/tests/sva/runtest.sh b/tests/sva/runtest.sh index db6c37011..6a855188f 100644 --- a/tests/sva/runtest.sh +++ b/tests/sva/runtest.sh @@ -65,10 +65,10 @@ elif [ -f $prefix.sv ]; then generate_sby fail > ${prefix}_fail.sby # Check that SBY is up to date enough for this yosys version - if sby --help | grep -q -e '--status'; then + if ${SBY} --help | grep -q -e '--status'; then set -x - sby --yosys ${YOSYS} -f ${prefix}_pass.sby - sby --yosys ${YOSYS} -f ${prefix}_fail.sby + ${SBY} --yosys ${YOSYS} -f ${prefix}_pass.sby + ${SBY} --yosys ${YOSYS} -f ${prefix}_fail.sby else echo "sva test '${prefix}' requires an up to date SBY, skipping" fi @@ -76,9 +76,9 @@ else generate_sby pass > ${prefix}.sby # Check that SBY is up to date enough for this yosys version - if sby --help | grep -q -e '--status'; then + if ${SBY} --help | grep -q -e '--status'; then set -x - sby --yosys ${YOSYS} -f ${prefix}.sby + ${SBY} --yosys ${YOSYS} -f ${prefix}.sby else echo "sva test '${prefix}' requires an up to date SBY, skipping" fi From 6f111118de5faee1c1cfba0aba1955756adae7bb Mon Sep 17 00:00:00 2001 From: junyao Date: Tue, 26 May 2026 00:56:07 +0800 Subject: [PATCH 20/30] proc: ignore nosync temporaries in always_latch checks --- passes/proc/proc_dlatch.cc | 11 +++++++++-- tests/various/svalways.sh | 14 ++++++++++++++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index 5e07dbcb0..50e64f482 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -395,10 +395,17 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) int offset = 0; for (auto chunk : nolatches_bits.first.chunks()) { SigSpec lhs = chunk, rhs = nolatches_bits.second.extract(offset, chunk.width); - if (proc->get_bool_attribute(ID::always_latch)) + bool is_nosync = true; + for (auto bit : lhs) + if (bit.wire == nullptr || !bit.wire->get_bool_attribute(ID::nosync)) { + is_nosync = false; + break; + } + + if (proc->get_bool_attribute(ID::always_latch) && !is_nosync) log_error("No latch inferred for signal `%s.%s' from always_latch process `%s.%s'.\n", db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); - else + else if (!is_nosync) log("No latch inferred for signal `%s.%s' from process `%s.%s'.\n", db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); for (auto &bit : lhs) { diff --git a/tests/various/svalways.sh b/tests/various/svalways.sh index b73786735..80cd234d4 100755 --- a/tests/various/svalways.sh +++ b/tests/various/svalways.sh @@ -18,6 +18,20 @@ always_latch endmodule EOT +# Good case: dynamic memory writes in always_latch create nosync mem2reg +# temporaries, but only the memory words themselves should be checked for +# latch inference. +${YOSYS} -f "verilog -sv" -qp proc - < Date: Thu, 28 May 2026 14:50:11 +1200 Subject: [PATCH 21/30] opt_clean: Set group for docs gen --- passes/opt/opt_clean/opt_clean.cc | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/passes/opt/opt_clean/opt_clean.cc b/passes/opt/opt_clean/opt_clean.cc index 87597d721..24085c34e 100644 --- a/passes/opt/opt_clean/opt_clean.cc +++ b/passes/opt/opt_clean/opt_clean.cc @@ -19,6 +19,7 @@ #include "kernel/register.h" #include "kernel/log.h" +#include "kernel/log_help.h" #include "passes/opt/opt_clean/opt_clean.h" USING_YOSYS_NAMESPACE @@ -43,6 +44,12 @@ void rmunused_module(RTLIL::Module *module, bool rminit, CleanRunContext &clean_ struct OptCleanPass : public Pass { OptCleanPass() : Pass("opt_clean", "remove unused cells and wires") { } + bool formatted_help() override + { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/opt"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -99,6 +106,12 @@ struct OptCleanPass : public Pass { struct CleanPass : public Pass { CleanPass() : Pass("clean", "remove unused cells and wires") { } + bool formatted_help() override + { + auto *help = PrettyHelp::get_current(); + help->set_group("passes/opt"); + return false; + } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| From d6106f141cc66c116c79cdc85bdf16327c43bed8 Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 27 May 2026 13:19:51 +0200 Subject: [PATCH 22/30] Add matching for fused mac operations for Nexus (fix #5906). --- techlibs/lattice/Makefile.inc | 8 ++ techlibs/lattice/dsp_map_nexus.v | 89 +++++++++++++ techlibs/lattice/lattice_dsp_nexus.cc | 36 ++++++ techlibs/lattice/lattice_dsp_nexus.pmg | 165 +++++++++++++++++++++++++ techlibs/lattice/synth_lattice.cc | 3 + tests/arch/nexus/fuse_mac.sv | 76 ++++++++++++ tests/arch/nexus/fuse_mac.ys | 35 ++++++ 7 files changed, 412 insertions(+) create mode 100644 techlibs/lattice/lattice_dsp_nexus.cc create mode 100644 techlibs/lattice/lattice_dsp_nexus.pmg create mode 100644 tests/arch/nexus/fuse_mac.sv create mode 100644 tests/arch/nexus/fuse_mac.ys diff --git a/techlibs/lattice/Makefile.inc b/techlibs/lattice/Makefile.inc index 9084472cf..1fb150e6c 100644 --- a/techlibs/lattice/Makefile.inc +++ b/techlibs/lattice/Makefile.inc @@ -1,6 +1,7 @@ OBJS += techlibs/lattice/synth_lattice.o OBJS += techlibs/lattice/lattice_gsr.o +OBJS += techlibs/lattice/lattice_dsp_nexus.o $(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_ff.vh)) $(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_io.vh)) @@ -50,3 +51,10 @@ $(eval $(call add_share_file_and_rename,share/ecp5,techlibs/lattice/cells_bb_ecp $(eval $(call add_share_file,share/nexus,techlibs/lattice/parse_init.vh)) $(eval $(call add_share_file_and_rename,share/nexus,techlibs/lattice/cells_sim_nexus.v,cells_sim.v)) $(eval $(call add_share_file_and_rename,share/nexus,techlibs/lattice/cells_bb_nexus.v,cells_xtra.v)) + +techlibs/lattice/%_pm.h: passes/pmgen/pmgen.py techlibs/lattice/%.pmg + $(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p $(notdir $*) $(filter-out $<,$^) + +GENFILES += techlibs/lattice/lattice_dsp_nexus_pm.h +techlibs/lattice/lattice_dsp_nexus.o: techlibs/lattice/lattice_dsp_nexus_pm.h +$(eval $(call add_extra_objs,techlibs/lattice/lattice_dsp_nexus_pm.h)) diff --git a/techlibs/lattice/dsp_map_nexus.v b/techlibs/lattice/dsp_map_nexus.v index b12528309..35caacd10 100644 --- a/techlibs/lattice/dsp_map_nexus.v +++ b/techlibs/lattice/dsp_map_nexus.v @@ -77,3 +77,92 @@ module \$__NX_MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y); .Z(Y) ); endmodule + +module \$__NX_MAC18X18 (A, B, C, Y); + + parameter A_WIDTH = 18; + parameter B_WIDTH = 18; + parameter C_WIDTH = 48; + parameter Y_WIDTH = 48; + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter SUBTRACT = 0; + input [17:0] A; + input [17:0] B; + input [47:0] C; + output [47:0] Y; + wire [53:0] Z_out; + assign Y = Z_out[47:0]; + + MULTADDSUB18X18 #( + .REGINPUTA("BYPASS"), + .REGINPUTB("BYPASS"), + .REGINPUTC("BYPASS"), + .REGOUTPUT("BYPASS") + ) _TECHMAP_REPLACE_ ( + .A(A), + .B(B), + .C({6'b0, C}), + .SIGNED(A_SIGNED ? 1'b1 : 1'b0), + .ADDSUB(SUBTRACT ? 1'b1 : 1'b0), + .Z(Z_out) + ); +endmodule + +module \$__NX_PREADD18X18 (A, B, C, Y, CLK); + + parameter PIPELINED = 0; + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter C_SIGNED = 0; + input [17:0] A; + input [17:0] B; + input [17:0] C; + input CLK; + output [47:0] Y; + wire [35:0] Z_out; + assign Y = A_SIGNED ? {{12{Z_out[35]}}, Z_out} : {12'b0, Z_out}; + + MULTPREADD18X18 #( + .REGINPUTA("BYPASS"), + .REGINPUTB("BYPASS"), + .REGINPUTC("BYPASS"), + .REGOUTPUT(PIPELINED ? "REGISTER" : "BYPASS") + ) _TECHMAP_REPLACE_ ( + .A(A), + .B(B), + .C(C), + .CLK(CLK), + .SIGNEDA(A_SIGNED ? 1'b1 : 1'b0), + .SIGNEDB(B_SIGNED ? 1'b1 : 1'b0), + .SIGNEDC(C_SIGNED ? 1'b1 : 1'b0), + .Z(Z_out) + ); +endmodule + +module \$__NX_MAC9X9WIDE_4LANE (A0, B0, A1, B1, A2, B2, A3, B3, Y); + + parameter SIGNED = 0; + input [8:0] A0, B0, A1, B1, A2, B2, A3, B3; + output [47:0] Y; + wire [53:0] Z_out; + assign Y = Z_out[47:0]; + + MULTADDSUB9X9WIDE #( + .REGINPUTAB0("BYPASS"), + .REGINPUTAB1("BYPASS"), + .REGINPUTAB2("BYPASS"), + .REGINPUTAB3("BYPASS"), + .REGINPUTC("BYPASS"), + .REGOUTPUT("BYPASS") + ) _TECHMAP_REPLACE_ ( + .A0(A0), .B0(B0), + .A1(A1), .B1(B1), + .A2(A2), .B2(B2), + .A3(A3), .B3(B3), + .C(54'b0), + .SIGNED(SIGNED ? 1'b1 : 1'b0), + .ADDSUB(4'b0000), + .Z(Z_out) + ); +endmodule diff --git a/techlibs/lattice/lattice_dsp_nexus.cc b/techlibs/lattice/lattice_dsp_nexus.cc new file mode 100644 index 000000000..d072c552d --- /dev/null +++ b/techlibs/lattice/lattice_dsp_nexus.cc @@ -0,0 +1,36 @@ +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#include "techlibs/lattice/lattice_dsp_nexus_pm.h" + +struct LatticeDspNexusPass : public Pass { + LatticeDspNexusPass() : Pass("lattice_dsp_nexus", "Lattice Nexus DSP inference") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" lattice_dsp_nexus [options] [selection]\n"); + log("\n"); + log("Infer Lattice Nexus sysDSP macrocells (MULTADDSUB18X18, MULTPREADD18X18,\n"); + log("MULTADDSUB9X9WIDE) from MAC and dot-product patterns.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing LATTICE_DSP_NEXUS pass.\n"); + extra_args(args, 1, design); + + for (auto module : design->selected_modules()) { + lattice_dsp_nexus_pm pm(module, module->cells()); + + pm.run_nexus_mac9_4lane(); + pm.run_nexus_mac18(); + pm.run_nexus_preadd18(); + } + } +} LatticeDspNexusPass; + +PRIVATE_NAMESPACE_END \ No newline at end of file diff --git a/techlibs/lattice/lattice_dsp_nexus.pmg b/techlibs/lattice/lattice_dsp_nexus.pmg new file mode 100644 index 000000000..73587b91c --- /dev/null +++ b/techlibs/lattice/lattice_dsp_nexus.pmg @@ -0,0 +1,165 @@ +pattern nexus_mac18 + +match mul + select mul->type.in($mul) + select GetSize(port(mul, \A)) <= 18 + select GetSize(port(mul, \B)) <= 18 + select GetSize(port(mul, \Y)) <= 48 +endmatch + +match add + select add->type.in($add, $sub) + select GetSize(port(add, \Y)) <= 48 + choice AB {\A, \B} + index port(add, AB)[0] === port(mul, \Y)[0] +endmatch + +code + SigSpec mul_out = port(mul, \Y); + IdString add_AB; + Cell *mac = module->addCell(NEW_ID, "$__NX_MAC18X18"); + IdString add_C = (add_AB == \A) ? \B : \A; + + mac->setPort(\A, port(mul, \A)); + mac->setPort(\B, port(mul, \B)); + mac->setPort(\C, port(add, add_C)); + mac->setPort(\Y, port(add, \Y)); + mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED)); + mac->setParam(\B_SIGNED, mul->getParam(\B_SIGNED)); + mac->setParam(\SUBTRACT, add->type == $sub ? State::S1 : State::S0); + + autoremove(mul); + autoremove(add); + + accept; +endcode + +pattern nexus_preadd18 + +match preadd + select preadd->type.in($add, $sub) + select GetSize(port(preadd, \Y)) <= 19 +endmatch + +match mul + select mul->type.in($mul) + select GetSize(port(mul, \Y)) <= 48 + choice mul_AB {\A, \B} + index port(mul, mul_AB)[0] === port(preadd, \Y)[0] +endmatch + +match pipe_ff + select pipe_ff->type.in($dff, $dffe, $sdff, $sdffe) + index port(pipe_ff, \D)[0] === port(mul, \Y)[0] + optional +endmatch + +code + SigSpec preadd_out = port(preadd, \Y); + IdString actual_mul_AB; + Cell *mac = module->addCell(NEW_ID, "$__NX_PREADD18X18"); + + IdString mul_other = (actual_mul_AB == \A) ? \B : \A; + IdString sgn_AC = (mul_other == \A) ? \B_SIGNED : \A_SIGNED; + IdString sgn_B = (mul_other == \A) ? \A_SIGNED : \B_SIGNED; + + SigSpec sig_A = port(preadd, \A); + SigSpec sig_C = port(preadd, \B); + SigSpec sig_B = port(mul, mul_other); + + sig_A.extend_u0(18, false); + sig_C.extend_u0(18, false); + sig_B.extend_u0(18, false); + + mac->setPort(\A, sig_A.extract(0, 18)); + mac->setPort(\C, sig_C.extract(0, 18)); + mac->setPort(\B, sig_B.extract(0, 18)); + + if (pipe_ff) { + mac->setPort(\Y, port(pipe_ff, \Q)); + mac->setPort(\CLK, port(pipe_ff, \CLK)); + mac->setParam(\PIPELINED, State::S1); + } else { + mac->setPort(\Y, port(mul, \Y)); + mac->setPort(\CLK, State::S0); + mac->setParam(\PIPELINED, State::S0); + } + + mac->setParam(\A_SIGNED, mul->getParam(sgn_AC)); + mac->setParam(\B_SIGNED, mul->getParam(sgn_B)); + mac->setParam(\C_SIGNED, mul->getParam(sgn_AC)); + + if (pipe_ff) autoremove(pipe_ff); + autoremove(mul); + autoremove(preadd); + accept; +endcode + +pattern nexus_mac9_4lane + +match add_top + select add_top->type == $add +endmatch + +match add_mid + select add_mid->type == $add + index port(add_mid, \Y)[0] === port(add_top, \A)[0] +endmatch + +match add_bot + select add_bot->type == $add + index port(add_bot, \Y)[0] === port(add_mid, \A)[0] +endmatch + +match mul3 + select mul3->type == $mul + select GetSize(port(mul3, \A)) <= 9 && GetSize(port(mul3, \B)) <= 9 + index port(mul3, \Y)[0] === port(add_top, \B)[0] +endmatch + +match mul2 + select mul2->type == $mul + select GetSize(port(mul2, \A)) <= 9 && GetSize(port(mul2, \B)) <= 9 + index port(mul2, \Y)[0] === port(add_mid, \B)[0] +endmatch + +match mul1 + select mul1->type == $mul + select GetSize(port(mul1, \A)) <= 9 && GetSize(port(mul1, \B)) <= 9 + index port(mul1, \Y)[0] === port(add_bot, \B)[0] +endmatch + +match mul0 + select mul0->type == $mul + select GetSize(port(mul0, \A)) <= 9 && GetSize(port(mul0, \B)) <= 9 + index port(mul0, \Y)[0] === port(add_bot, \A)[0] +endmatch + +code + Cell *mac = module->addCell(NEW_ID, "$__NX_MAC9X9WIDE_4LANE"); + bool is_signed = mul0->getParam(\A_SIGNED).as_bool(); + auto ext9 = [&](SigSpec s) { + s.extend_u0(9, is_signed); + return s; + }; + + mac->setPort(\A0, ext9(port(mul0, \A))); + mac->setPort(\B0, ext9(port(mul0, \B))); + mac->setPort(\A1, ext9(port(mul1, \A))); + mac->setPort(\B1, ext9(port(mul1, \B))); + mac->setPort(\A2, ext9(port(mul2, \A))); + mac->setPort(\B2, ext9(port(mul2, \B))); + mac->setPort(\A3, ext9(port(mul3, \A))); + mac->setPort(\B3, ext9(port(mul3, \B))); + mac->setPort(\Y, port(add_top, \Y)); + mac->setParam(\SIGNED, mul0->getParam(\A_SIGNED)); + + autoremove(add_top); + autoremove(add_mid); + autoremove(add_bot); + autoremove(mul0); + autoremove(mul1); + autoremove(mul2); + autoremove(mul3); + accept; +endcode diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc index 382dae3d8..43fb7b1c2 100644 --- a/techlibs/lattice/synth_lattice.cc +++ b/techlibs/lattice/synth_lattice.cc @@ -425,9 +425,12 @@ struct SynthLatticePass : public ScriptPass run("opt_clean"); if (help_mode) { + run("lattice_dsp_nexus", "(only if -family lifcl/lfd2nx and unless -nodsp)"); run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp)"); run("techmap -map +/lattice/dsp_map" + dsp_map + ".v", "(unless -nodsp)"); } else if (have_dsp && !nodsp) { + if (is_nexus) + run("lattice_dsp_nexus"); for (const auto &rule : dsp_rules) { run(stringf("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d -D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_NAME=%s", rule.a_maxwidth, rule.b_maxwidth, rule.a_minwidth, rule.b_minwidth, rule.prim)); diff --git a/tests/arch/nexus/fuse_mac.sv b/tests/arch/nexus/fuse_mac.sv new file mode 100644 index 000000000..cf16bd261 --- /dev/null +++ b/tests/arch/nexus/fuse_mac.sv @@ -0,0 +1,76 @@ +// https://github.com/YosysHQ/yosys/issues/5906 + +module mac ( + input bit clk, rst, + input bit [17:0] a, b, + input bit clear, + output bit [47:0] p +); + bit [17:0] a_r, b_r; bit clear_r; bit [47:0] p_r; + always_ff @(posedge clk) begin + if (rst) begin a_r<=0; b_r<=0; clear_r<=0; p_r<=0; end + else begin + a_r<=a; b_r<=b; clear_r<=clear; + p_r <= clear_r ? 48'(a_r*b_r) : 48'(p_r + 48'(a_r*b_r)); + end + end + assign p = p_r; +endmodule + +module madd_pre ( + input bit clk, rst, + input bit [17:0] a, b, c, d, + output bit [47:0] p +); + bit [17:0] a_r, b_r, c_r, d_r; bit [47:0] m_r, p_r; + always_ff @(posedge clk) begin + if (rst) begin a_r<=0; b_r<=0; c_r<=0; d_r<=0; m_r<=0; p_r<=0; end + else begin + a_r<=a; b_r<=b; c_r<=c; d_r<=d; + m_r <= 48'((a_r - d_r) * b_r); + p_r <= 48'(m_r + 48'(c_r)); + end + end + assign p = p_r; +endmodule + +module dot4 ( + input bit clk, rst, + input bit [8:0] a0, b0, a1, b1, a2, b2, a3, b3, + output bit [19:0] p +); + bit [8:0] a0_r, b0_r, a1_r, b1_r, a2_r, b2_r, a3_r, b3_r; + bit [19:0] p_r; + always_ff @(posedge clk) begin + if (rst) begin + a0_r<=0; b0_r<=0; a1_r<=0; b1_r<=0; + a2_r<=0; b2_r<=0; a3_r<=0; b3_r<=0; + p_r<=0; + end else begin + a0_r<=a0; b0_r<=b0; a1_r<=a1; b1_r<=b1; + a2_r<=a2; b2_r<=b2; a3_r<=a3; b3_r<=b3; + p_r <= 20'(20'(a0_r*b0_r) + 20'(a1_r*b1_r) + 20'(a2_r*b2_r) + 20'(a3_r*b3_r)); + end + end + assign p = p_r; +endmodule + +// Oversized 24x24 MAC +module neg_mac24 (input clk, clear, input [23:0] a, b, output [47:0] p); + reg [23:0] a_r, b_r; reg [47:0] p_r; reg clear_r; + always_ff @(posedge clk) begin + a_r <= a; b_r <= b; clear_r <= clear; + p_r <= clear_r ? 48'(a_r*b_r) : 48'(p_r + 48'(a_r*b_r)); + end + assign p = p_r; +endmodule + +// Dot product with mixed 9x9 and 18x18 lanes +module neg_dot_mixed (input clk, input [8:0] a0,b0,a1,b1, input [17:0] a2, b2, output [35:0] p); + reg [8:0] a0_r,b0_r,a1_r,b1_r; reg [17:0] a2_r, b2_r; reg [35:0] p_r; + always_ff @(posedge clk) begin + a0_r<=a0; b0_r<=b0; a1_r<=a1; b1_r<=b1; a2_r<=a2; b2_r<=b2; + p_r <= 36'(36'(a0_r*b0_r) + 36'(a1_r*b1_r) + 36'(a2_r*b2_r)); + end + assign p = p_r; +endmodule diff --git a/tests/arch/nexus/fuse_mac.ys b/tests/arch/nexus/fuse_mac.ys new file mode 100644 index 000000000..e3e117130 --- /dev/null +++ b/tests/arch/nexus/fuse_mac.ys @@ -0,0 +1,35 @@ +read_verilog -sv fuse_mac.sv + +design -save pristine + +# 18x18 MAC +design -load pristine +hierarchy -top mac; +synth_nexus -family lifcl -top mac +select -assert-count 1 t:MULTADDSUB18X18 +select -assert-count 0 t:CCU2 + +# 18x18 pre-add MAC +design -load pristine +hierarchy -top madd_pre; +synth_nexus -family lifcl -top madd_pre +select -assert-count 1 t:MULTPREADD18X18 + +# 4-lane 9x9 dot product +design -load pristine +hierarchy -top dot4; +synth_nexus -family lifcl -top dot4 +select -assert-count 1 t:MULTADDSUB9X9WIDE + +# 24x24 MAC +design -load pristine +hierarchy -top neg_mac24; +synth_nexus -family lifcl -top neg_mac24 +select -assert-count 0 t:MULTADDSUB18X18 + +# mixed +design -load pristine +hierarchy -top neg_dot_mixed; +synth_nexus -family lifcl -top neg_dot_mixed +select -assert-count 0 t:MULTADDSUB9X9WIDE +select -assert-count 2 t:MULTADDSUB18X18 From 7fef67a1413c463af027265aa5f5c514dc6ca43a Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 27 May 2026 15:09:27 +0200 Subject: [PATCH 23/30] Simplify nexus map. --- techlibs/lattice/dsp_map_nexus.v | 29 ++++++----------------------- 1 file changed, 6 insertions(+), 23 deletions(-) diff --git a/techlibs/lattice/dsp_map_nexus.v b/techlibs/lattice/dsp_map_nexus.v index 35caacd10..61d2d96a8 100644 --- a/techlibs/lattice/dsp_map_nexus.v +++ b/techlibs/lattice/dsp_map_nexus.v @@ -78,7 +78,7 @@ module \$__NX_MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y); ); endmodule -module \$__NX_MAC18X18 (A, B, C, Y); +module \$__NX_MAC18X18 (input [17:0] A, input [17:0] B, input [47:0] C, output [53:0] Y); parameter A_WIDTH = 18; parameter B_WIDTH = 18; @@ -87,12 +87,6 @@ module \$__NX_MAC18X18 (A, B, C, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter SUBTRACT = 0; - input [17:0] A; - input [17:0] B; - input [47:0] C; - output [47:0] Y; - wire [53:0] Z_out; - assign Y = Z_out[47:0]; MULTADDSUB18X18 #( .REGINPUTA("BYPASS"), @@ -105,23 +99,16 @@ module \$__NX_MAC18X18 (A, B, C, Y); .C({6'b0, C}), .SIGNED(A_SIGNED ? 1'b1 : 1'b0), .ADDSUB(SUBTRACT ? 1'b1 : 1'b0), - .Z(Z_out) + .Z(Y) ); endmodule -module \$__NX_PREADD18X18 (A, B, C, Y, CLK); +module \$__NX_PREADD18X18 (input [17:0] A, input [17:0] B, input [17:0] C, input CLK, output [35:0] Y); parameter PIPELINED = 0; parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter C_SIGNED = 0; - input [17:0] A; - input [17:0] B; - input [17:0] C; - input CLK; - output [47:0] Y; - wire [35:0] Z_out; - assign Y = A_SIGNED ? {{12{Z_out[35]}}, Z_out} : {12'b0, Z_out}; MULTPREADD18X18 #( .REGINPUTA("BYPASS"), @@ -136,17 +123,13 @@ module \$__NX_PREADD18X18 (A, B, C, Y, CLK); .SIGNEDA(A_SIGNED ? 1'b1 : 1'b0), .SIGNEDB(B_SIGNED ? 1'b1 : 1'b0), .SIGNEDC(C_SIGNED ? 1'b1 : 1'b0), - .Z(Z_out) + .Z(Y) ); endmodule -module \$__NX_MAC9X9WIDE_4LANE (A0, B0, A1, B1, A2, B2, A3, B3, Y); +module \$__NX_MAC9X9WIDE_4LANE (input [8:0] A0, B0, A1, B1, A2, B2, A3, B3, output [53:0] Y); parameter SIGNED = 0; - input [8:0] A0, B0, A1, B1, A2, B2, A3, B3; - output [47:0] Y; - wire [53:0] Z_out; - assign Y = Z_out[47:0]; MULTADDSUB9X9WIDE #( .REGINPUTAB0("BYPASS"), @@ -163,6 +146,6 @@ module \$__NX_MAC9X9WIDE_4LANE (A0, B0, A1, B1, A2, B2, A3, B3, Y); .C(54'b0), .SIGNED(SIGNED ? 1'b1 : 1'b0), .ADDSUB(4'b0000), - .Z(Z_out) + .Z(Y) ); endmodule From 14140126761cc94fe66f5af87bd588b4cddd5dbd Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 27 May 2026 15:09:50 +0200 Subject: [PATCH 24/30] Add sign and op checks. --- techlibs/lattice/lattice_dsp_nexus.pmg | 175 +++++++++++++++---------- 1 file changed, 109 insertions(+), 66 deletions(-) diff --git a/techlibs/lattice/lattice_dsp_nexus.pmg b/techlibs/lattice/lattice_dsp_nexus.pmg index 73587b91c..5fb828bb9 100644 --- a/techlibs/lattice/lattice_dsp_nexus.pmg +++ b/techlibs/lattice/lattice_dsp_nexus.pmg @@ -15,21 +15,35 @@ match add endmatch code - SigSpec mul_out = port(mul, \Y); - IdString add_AB; - Cell *mac = module->addCell(NEW_ID, "$__NX_MAC18X18"); - IdString add_C = (add_AB == \A) ? \B : \A; + if (mul->getParam(\A_SIGNED).as_bool() != mul->getParam(\B_SIGNED).as_bool()) { + reject; + } - mac->setPort(\A, port(mul, \A)); - mac->setPort(\B, port(mul, \B)); - mac->setPort(\C, port(add, add_C)); - mac->setPort(\Y, port(add, \Y)); - mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED)); - mac->setParam(\B_SIGNED, mul->getParam(\B_SIGNED)); - mac->setParam(\SUBTRACT, add->type == $sub ? State::S1 : State::S0); + { + SigSpec mul_out = port(mul, \Y); + IdString add_AB; - autoremove(mul); - autoremove(add); + if (GetSize(port(add, \A)) >= GetSize(mul_out) && port(add, \A).extract(0, GetSize(mul_out)) == mul_out) { + add_AB = \A; + } else if (GetSize(port(add, \B)) >= GetSize(mul_out) && port(add, \B).extract(0, GetSize(mul_out)) == mul_out) { + add_AB = \B; + } else { + reject; + } + + Cell *mac = module->addCell(NEW_ID, "$__NX_MAC18X18"); + IdString add_C = (add_AB == \A) ? \B : \A; + + mac->setPort(\A, port(mul, \A)); + mac->setPort(\B, port(mul, \B)); + mac->setPort(\C, port(add, add_C)); + mac->setPort(\Y, port(add, \Y)); + mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED)); + mac->setParam(\SUBTRACT, add->type == $sub ? State::S1 : State::S0); + + autoremove(mul); + autoremove(add); + } accept; endcode @@ -57,41 +71,53 @@ endmatch code SigSpec preadd_out = port(preadd, \Y); IdString actual_mul_AB; - Cell *mac = module->addCell(NEW_ID, "$__NX_PREADD18X18"); - IdString mul_other = (actual_mul_AB == \A) ? \B : \A; - IdString sgn_AC = (mul_other == \A) ? \B_SIGNED : \A_SIGNED; - IdString sgn_B = (mul_other == \A) ? \A_SIGNED : \B_SIGNED; - - SigSpec sig_A = port(preadd, \A); - SigSpec sig_C = port(preadd, \B); - SigSpec sig_B = port(mul, mul_other); - - sig_A.extend_u0(18, false); - sig_C.extend_u0(18, false); - sig_B.extend_u0(18, false); - - mac->setPort(\A, sig_A.extract(0, 18)); - mac->setPort(\C, sig_C.extract(0, 18)); - mac->setPort(\B, sig_B.extract(0, 18)); - - if (pipe_ff) { - mac->setPort(\Y, port(pipe_ff, \Q)); - mac->setPort(\CLK, port(pipe_ff, \CLK)); - mac->setParam(\PIPELINED, State::S1); + if (GetSize(port(mul, \A)) >= GetSize(preadd_out) && port(mul, \A).extract(0, GetSize(preadd_out)) == preadd_out) { + actual_mul_AB = \A; + } else if (GetSize(port(mul, \B)) >= GetSize(preadd_out) && port(mul, \B).extract(0, GetSize(preadd_out)) == preadd_out) { + actual_mul_AB = \B; } else { - mac->setPort(\Y, port(mul, \Y)); - mac->setPort(\CLK, State::S0); - mac->setParam(\PIPELINED, State::S0); + reject; } - mac->setParam(\A_SIGNED, mul->getParam(sgn_AC)); - mac->setParam(\B_SIGNED, mul->getParam(sgn_B)); - mac->setParam(\C_SIGNED, mul->getParam(sgn_AC)); + { + Cell *mac = module->addCell(NEW_ID, "$__NX_PREADD18X18"); + + IdString mul_other = (actual_mul_AB == \A) ? \B : \A; + IdString sgn_AC = (mul_other == \A) ? \B_SIGNED : \A_SIGNED; + IdString sgn_B = (mul_other == \A) ? \A_SIGNED : \B_SIGNED; + + SigSpec sig_A = port(preadd, \A); + SigSpec sig_C = port(preadd, \B); + SigSpec sig_B = port(mul, mul_other); + + sig_A.extend_u0(18, false); + sig_C.extend_u0(18, false); + sig_B.extend_u0(18, false); + + mac->setPort(\A, sig_A.extract(0, 18)); + mac->setPort(\C, sig_C.extract(0, 18)); + mac->setPort(\B, sig_B.extract(0, 18)); + + if (pipe_ff) { + mac->setPort(\Y, port(pipe_ff, \Q)); + mac->setPort(\CLK, port(pipe_ff, \CLK)); + mac->setParam(\PIPELINED, State::S1); + } else { + mac->setPort(\Y, port(mul, \Y)); + mac->setPort(\CLK, State::S0); + mac->setParam(\PIPELINED, State::S0); + } + + mac->setParam(\A_SIGNED, mul->getParam(sgn_AC)); + mac->setParam(\B_SIGNED, mul->getParam(sgn_B)); + mac->setParam(\C_SIGNED, mul->getParam(sgn_AC)); + + if (pipe_ff) autoremove(pipe_ff); + autoremove(mul); + autoremove(preadd); + } - if (pipe_ff) autoremove(pipe_ff); - autoremove(mul); - autoremove(preadd); accept; endcode @@ -136,30 +162,47 @@ match mul0 endmatch code - Cell *mac = module->addCell(NEW_ID, "$__NX_MAC9X9WIDE_4LANE"); bool is_signed = mul0->getParam(\A_SIGNED).as_bool(); - auto ext9 = [&](SigSpec s) { - s.extend_u0(9, is_signed); - return s; - }; - mac->setPort(\A0, ext9(port(mul0, \A))); - mac->setPort(\B0, ext9(port(mul0, \B))); - mac->setPort(\A1, ext9(port(mul1, \A))); - mac->setPort(\B1, ext9(port(mul1, \B))); - mac->setPort(\A2, ext9(port(mul2, \A))); - mac->setPort(\B2, ext9(port(mul2, \B))); - mac->setPort(\A3, ext9(port(mul3, \A))); - mac->setPort(\B3, ext9(port(mul3, \B))); - mac->setPort(\Y, port(add_top, \Y)); - mac->setParam(\SIGNED, mul0->getParam(\A_SIGNED)); + if ( + mul0->getParam(\B_SIGNED).as_bool() != is_signed || + mul1->getParam(\A_SIGNED).as_bool() != is_signed || + mul1->getParam(\B_SIGNED).as_bool() != is_signed || + mul2->getParam(\A_SIGNED).as_bool() != is_signed || + mul2->getParam(\B_SIGNED).as_bool() != is_signed || + mul3->getParam(\A_SIGNED).as_bool() != is_signed || + mul3->getParam(\B_SIGNED).as_bool() != is_signed + ) { + reject; + } + + { + Cell *mac = module->addCell(NEW_ID, "$__NX_MAC9X9WIDE_4LANE"); + + auto ext9 = [&](SigSpec s) { + s.extend_u0(9, is_signed); + return s; + }; + + mac->setPort(\A0, ext9(port(mul0, \A))); + mac->setPort(\B0, ext9(port(mul0, \B))); + mac->setPort(\A1, ext9(port(mul1, \A))); + mac->setPort(\B1, ext9(port(mul1, \B))); + mac->setPort(\A2, ext9(port(mul2, \A))); + mac->setPort(\B2, ext9(port(mul2, \B))); + mac->setPort(\A3, ext9(port(mul3, \A))); + mac->setPort(\B3, ext9(port(mul3, \B))); + mac->setPort(\Y, port(add_top, \Y)); + mac->setParam(\SIGNED, is_signed ? State::S1 : State::S0); + + autoremove(add_top); + autoremove(add_mid); + autoremove(add_bot); + autoremove(mul0); + autoremove(mul1); + autoremove(mul2); + autoremove(mul3); + } - autoremove(add_top); - autoremove(add_mid); - autoremove(add_bot); - autoremove(mul0); - autoremove(mul1); - autoremove(mul2); - autoremove(mul3); accept; -endcode +endcode \ No newline at end of file From d8587f44f0566b5d442216ed12860f03cd7a49e2 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 28 May 2026 11:13:29 +0200 Subject: [PATCH 25/30] Putting back some Makefile.conf --- tests/common.mk | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tests/common.mk b/tests/common.mk index ef6982514..0e85e9fb9 100644 --- a/tests/common.mk +++ b/tests/common.mk @@ -1,9 +1,16 @@ ROOT_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) BUILD_DIR ?= $(ROOT_DIR)/.. +ifneq ($(wildcard $(ROOT_DIR)/../Makefile.conf),) +include $(ROOT_DIR)/../Makefile.conf +endif SBY ?= sby YOSYS ?= $(BUILD_DIR)/yosys +ifneq ($(ABCEXTERNAL),) +ABC ?= $(ABCEXTERNAL) +else ABC ?= $(BUILD_DIR)/yosys-abc +endif YOSYS_FILTERLIB ?= $(BUILD_DIR)/yosys-filterlib YOSYS_CONFIG ?= $(BUILD_DIR)/yosys-config YOSYS_SMTBMC ?= $(BUILD_DIR)/yosys-smtbmc From 1d86b3cd6eba3516a27ad1af91f0eeab7b4d5d87 Mon Sep 17 00:00:00 2001 From: Patrick Urban Date: Thu, 28 May 2026 14:46:25 +0200 Subject: [PATCH 26/30] gatemate: add option to create 'scopename' attributes when flattening the netlist --- techlibs/gatemate/synth_gatemate.cc | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/techlibs/gatemate/synth_gatemate.cc b/techlibs/gatemate/synth_gatemate.cc index f7cdcbd12..6861b6780 100644 --- a/techlibs/gatemate/synth_gatemate.cc +++ b/techlibs/gatemate/synth_gatemate.cc @@ -56,6 +56,9 @@ struct SynthGateMatePass : public ScriptPass log(" -noflatten\n"); log(" do not flatten design before synthesis.\n"); log("\n"); + log(" -scopename\n"); + log(" create 'scopename' attributes when flattening the netlist.\n"); + log("\n"); log(" -nobram\n"); log(" do not use CC_BRAM_20K or CC_BRAM_40K cells in output netlist.\n"); log("\n"); @@ -94,7 +97,7 @@ struct SynthGateMatePass : public ScriptPass } string top_opt, vlog_file, json_file; - bool noflatten, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf, abc_new; + bool noflatten, scopename, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf, abc_new; void clear_flags() override { @@ -102,6 +105,7 @@ struct SynthGateMatePass : public ScriptPass vlog_file = ""; json_file = ""; noflatten = false; + scopename = false; nobram = false; noaddf = false; nomult = false; @@ -147,6 +151,10 @@ struct SynthGateMatePass : public ScriptPass noflatten = true; continue; } + if (args[argidx] == "-scopename") { + scopename = true; + continue; + } if (args[argidx] == "-nobram") { nobram = true; continue; @@ -220,7 +228,8 @@ struct SynthGateMatePass : public ScriptPass run("proc"); if (!noflatten) { run("check"); - run("flatten"); + std::string flatten_args = scopename ? " -scopename" : ""; + run("flatten" + flatten_args); } run("tribuf -logic"); run("deminout"); From 80bdbaa010d16a7602a1f36ff640cdb3c32081ed Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 29 May 2026 11:37:08 +0200 Subject: [PATCH 27/30] genrtlil: don't avoid emitting flops for nosync --- frontends/ast/genrtlil.cc | 12 ------------ tests/verilog/automatic_lifetime.ys | 5 +++++ 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 718d5aa23..f7c5bb7bd 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -406,18 +406,6 @@ struct AST_INTERNAL::ProcessGenerator if (GetSize(syncrule->signal) != 1) always->input_error("Found posedge/negedge event on a signal that is not 1 bit wide!\n"); addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true); - // Automatic (nosync) variables must not become flip-flops: remove - // them from clocked sync rules so that proc_dff does not infer - // an unnecessary register for a purely combinational temporary. - syncrule->actions.erase( - std::remove_if(syncrule->actions.begin(), syncrule->actions.end(), - [](const RTLIL::SigSig &ss) { - for (auto &chunk : ss.first.chunks()) - if (chunk.wire && chunk.wire->get_bool_attribute(ID::nosync)) - return true; - return false; - }), - syncrule->actions.end()); proc->syncs.push_back(syncrule); } if (proc->syncs.empty()) { diff --git a/tests/verilog/automatic_lifetime.ys b/tests/verilog/automatic_lifetime.ys index 84e21e088..7df02e67f 100644 --- a/tests/verilog/automatic_lifetime.ys +++ b/tests/verilog/automatic_lifetime.ys @@ -15,6 +15,7 @@ module t1(input a, b, c, output reg y); endmodule EOF proc +opt_clean async2sync # no state elements for tmp select -assert-none t:$dff t:$dlatch %% @@ -39,6 +40,7 @@ module t2(input [3:0] a, b, input sel, output reg [3:0] y, output reg co); endmodule EOF proc +opt_clean async2sync select -assert-none t:$dff t:$dlatch %% sat -verify -prove-asserts -show-all @@ -59,6 +61,7 @@ module t3(input clk, rst, input [7:0] data, output reg [7:0] result); endmodule EOF proc +opt_clean # Exactly one DFF (for result), zero latches, no DFF for tmp select -assert-count 1 t:$dff %% select -assert-none t:$dlatch %% @@ -80,6 +83,7 @@ module t4(input [7:0] a, b, input sub, output reg [7:0] y); endmodule EOF proc +opt_clean async2sync select -assert-none t:$dff t:$dlatch %% sat -verify -prove-asserts -show-all @@ -100,5 +104,6 @@ module t5(input en, d, output reg q); endmodule EOF proc +opt_clean # No latch for tmp — X propagates instead of old value select -assert-none t:$dff t:$dlatch %% From 904151acd8d4aa9878b7922e4239c20d3c590e31 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 1 Jun 2026 09:59:04 +0200 Subject: [PATCH 28/30] Fix wheels --- .github/workflows/wheels.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index 8139b5af5..9450534be 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -66,6 +66,7 @@ jobs: run: | mkdir -p bison curl -L https://ftpmirror.gnu.org/gnu/bison/bison-3.8.2.tar.gz | tar --strip-components=1 -xzC bison + sed -i 's/-Werror=unused//g' Makefile ## Software installed by default in GitHub Action Runner VMs: ## https://github.com/actions/runner-images - if: ${{ matrix.os.family == 'macos' }} From 86f2ddebce7e98ce7cacc27e8a5c14cb53b51b51 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 1 Jun 2026 17:01:26 +0200 Subject: [PATCH 29/30] Release version 0.66 --- CHANGELOG | 12 +++++++++++- Makefile | 4 ++-- docs/source/conf.py | 2 +- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 01faf44c2..5810cf08f 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,8 +2,18 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.65 .. Yosys 0.66-dev +Yosys 0.65 .. Yosys 0.66 -------------------------- + * Various + - C++ compiler with C++20 support is required. + - Please be aware that next release will also + migrate to CMake build system. + + * New commands and options + - Added "lattice_dsp_nexus" pass for Lattice Nexus + DSP inference. + - Added "-scopename" option to "synth_gatemate" pass + that is propagated to "flatten". Yosys 0.64 .. Yosys 0.65 -------------------------- diff --git a/Makefile b/Makefile index 6ee34070d..99a00fd40 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.65 +YOSYS_VER := 0.66 ifneq (, $(shell command -v git 2>/dev/null)) ifneq (, $(shell git rev-parse --git-dir 2>/dev/null)) @@ -170,7 +170,7 @@ ifneq (, $(shell git rev-parse --git-dir 2>/dev/null)) YOSYS_VER := $(YOSYS_VER)+$(GIT_COMMIT_COUNT) endif else - YOSYS_VER := $(YOSYS_VER)+post +# YOSYS_VER := $(YOSYS_VER)+post endif endif diff --git a/docs/source/conf.py b/docs/source/conf.py index b85c391db..92975d3df 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -6,7 +6,7 @@ import os project = 'YosysHQ Yosys' author = 'YosysHQ GmbH' copyright ='2026 YosysHQ GmbH' -yosys_ver = "0.65" +yosys_ver = "0.66" # select HTML theme html_theme = 'furo-ys' From 8bb194af22d1ced67bd96c6597c4a2898b6d89a5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 1 Jun 2026 18:23:28 +0200 Subject: [PATCH 30/30] Next dev cycle --- CHANGELOG | 3 +++ Makefile | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/CHANGELOG b/CHANGELOG index 5810cf08f..61b221bc9 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.66 .. Yosys 0.67-dev +-------------------------- + Yosys 0.65 .. Yosys 0.66 -------------------------- * Various diff --git a/Makefile b/Makefile index 99a00fd40..8bb1c0b2a 100644 --- a/Makefile +++ b/Makefile @@ -170,7 +170,7 @@ ifneq (, $(shell git rev-parse --git-dir 2>/dev/null)) YOSYS_VER := $(YOSYS_VER)+$(GIT_COMMIT_COUNT) endif else -# YOSYS_VER := $(YOSYS_VER)+post + YOSYS_VER := $(YOSYS_VER)+post endif endif