mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-02-16 05:41:45 +00:00
Code Activity

abc9: perform name preservation

Browse source
This commit is contained in:
Lofty 2026-02-11 14:06:53 +00:00
parent fba29ea8f1
commit fb2f3bdb4e
4 changed files with 45 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/techmap/abc9_exe.cc
View file

@ -248,11 +248,11 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
}
abc9_script += stringf("; &ps -l; &write -n %s/output.aig", tempdir_name);
if (design->scratchpad_get_bool("abc9.verify")) {
if (design->scratchpad_get_bool("abc9.verify", true)) {
if (dff_mode)
abc9_script += "; &verify -s";
else
abc9_script += "; &verify";
abc9_script += "; &verify -y";
}
abc9_script += "; time";
abc9_script = add_echos_to_abc9_cmd(abc9_script);

34
passes/techmap/aigmap.cc
View file

@ -17,8 +17,11 @@
*
*/
#include "kernel/rtlil.h"
#include "kernel/yosys.h"
#include "kernel/cellaigs.h"
#include "kernel/yosys_common.h"
#include <sstream>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -93,6 +96,7 @@ struct AigmapPass : public Pass {
vector<SigBit> sigs;
dict<pair<int, int>, SigBit> and_cache;
dict<pair<int, int>, SigBit> not_cache;
for (int node_idx = 0; node_idx < GetSize(aig.nodes); node_idx++)
{
@ -119,21 +123,37 @@ struct AigmapPass : public Pass {
if (and_cache.count(key))
bit = and_cache.at(key);
else {
bit = module->addWire(NEW_ID);
std::stringstream ss;
ss << log_id(cell->name) << "$" << node_idx;
bit = module->addWire(IdString(ss.str()));
auto gate = module->addAndGate(NEW_ID, A, B, bit);
if (select_mode)
new_sel.insert(gate->name);
and_cache.insert({key, bit});
}
}
}
if (node.inverter) {
SigBit new_bit = module->addWire(NEW_ID);
auto gate = module->addNotGate(NEW_ID, bit, new_bit);
bit = new_bit;
if (select_mode)
new_sel.insert(gate->name);
pair<int, int> key(node.left_parent, node.right_parent);
if (not_cache.count(key))
bit = not_cache.at(key);
else {
IdString name;
if (bit.wire != nullptr) {
std::stringstream ss;
ss << "\\~" << log_id(bit.wire) << "[" << bit.offset << "]" << "$" << (autoidx++);
name = IdString(ss.str());
} else {
name = NEW_ID;
}
SigBit new_bit = module->addWire(name);
auto gate = module->addNotGate(NEW_ID, bit, new_bit);
bit = new_bit;
if (select_mode)
new_sel.insert(gate->name);
not_cache.insert({key, bit});
}
}
skip_inverter: