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Added correct handling of $memwr priority

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This commit is contained in:
Clifford Wolf 2014-01-03 00:22:17 +01:00
parent 536e20bde1
commit fb2bf934dc
5 changed files with 42 additions and 2 deletions
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17
tests/simple/memory.v
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@ -1,4 +1,21 @@
module test00(clk, setA, setB, y);
input clk, setA, setB;
output y;
reg mem [1:0];
always @(posedge clk) begin
if (setA) mem[0] <= 0; // this is line 9
if (setB) mem[0] <= 1; // this is line 10
end
assign y = mem[0];
endmodule
// ----------------------------------------------------------
module test01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
input clk, wr_en;