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https://github.com/YosysHQ/yosys
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Added correct handling of $memwr priority
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parent
536e20bde1
commit
fb2bf934dc
5 changed files with 42 additions and 2 deletions
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@ -20,9 +20,19 @@
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <sstream>
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#include <algorithm>
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#include <stdlib.h>
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#include <assert.h>
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static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
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{
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if (a->type == "$memrd" && b->type == "$memrd")
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return a->name < b->name;
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if (a->type == "$memrd" || b->type == "$memrd")
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return (a->type == "$memrd") < (b->type == "$memrd");
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return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int();
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}
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static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
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{
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log("Collecting $memrd and $memwr for memory `%s' in module `%s':\n",
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@ -48,11 +58,18 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
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RTLIL::SigSpec sig_rd_data;
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std::vector<std::string> del_cell_ids;
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std::vector<RTLIL::Cell*> memcells;
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for (auto &cell_it : module->cells)
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{
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for (auto &cell_it : module->cells) {
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RTLIL::Cell *cell = cell_it.second;
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if ((cell->type == "$memwr" || cell->type == "$memrd") && cell->parameters["\\MEMID"].decode_string() == memory->name)
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memcells.push_back(cell);
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}
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std::sort(memcells.begin(), memcells.end(), memcells_cmp);
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for (auto cell : memcells)
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{
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if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name)
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{
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wr_ports++;
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