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Added correct handling of $memwr priority

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Clifford Wolf 2014-01-03 00:22:17 +01:00
parent 536e20bde1
commit fb2bf934dc
5 changed files with 42 additions and 2 deletions
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manual/CHAPTER_CellLib.tex
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@ -272,6 +272,9 @@ the \B{CLK} input is not used.
\item \B{CLK\_POLARITY} \\
Clock is active on positive edge if this parameter has the value {\tt 1'b1} and on the negative
edge if this parameter is {\tt 1'b0}.
\item \B{PRIORITY} \\
The cell with the higher integer value in this parameter wins a write conflict.
\end{itemize}
The HDL frontend models a memory using RTLIL::Memory objects and asynchronous