mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00
Code Activity

Added correct handling of $memwr priority

Browse source
This commit is contained in:
Clifford Wolf 2014-01-03 00:22:17 +01:00
parent 536e20bde1
commit fb2bf934dc
5 changed files with 42 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

1
kernel/rtlil.cc
View file

@ -567,6 +567,7 @@ namespace {
param("\\MEMID");
param("\\CLK_ENABLE");
param("\\CLK_POLARITY");
param("\\PRIORITY");
port("\\CLK", 1);
port("\\EN", 1);
port("\\ADDR", param("\\ABITS"));