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verilog: Support void functions

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The difference between void functions and tasks is that always_comb's
implicit sensitivity list behaves as if functions were inlined, but
ignores signals read only in tasks. This only matters for event based
simulation, and for synthesis we can treat a void function like a task.
This commit is contained in:
Jannis Harder 2023-03-20 12:50:14 +01:00
parent 61da330a38
commit fb1c2be76b
3 changed files with 56 additions and 1 deletions
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frontends/verilog/verilog_lexer.l
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@ -276,6 +276,7 @@ TIME_SCALE_SUFFIX [munpf]?s
"byte" { SV_KEYWORD(TOK_BYTE); }
"shortint" { SV_KEYWORD(TOK_SHORTINT); }
"longint" { SV_KEYWORD(TOK_LONGINT); }
"void" { SV_KEYWORD(TOK_VOID); }
"eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
"s_eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }