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autoname: rewrite

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This commit is contained in:
Emil J. Tywoniak 2026-07-17 12:02:43 +02:00
parent 9914b6fa25
commit fb0bb160ad
2 changed files with 216 additions and 94 deletions
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9
tests/various/autoname.ys
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@ -180,15 +180,16 @@ design -save order_test
# wires are named for being cell outputs
logger -expect log "Rename wire .d in top to or_Y" 1
logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
logger -expect log "Renamed 2 objects" 1
logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1
logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
logger -expect log "Renamed 4 objects" 1
debug autoname t:$or
logger -check-expected
# $name gets shortest name (otherwise bcd_$__unknown_B)
logger -expect log "Rename cell .name in top to a_.__unknown_A" 1
# another output wire
logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1
logger -expect log "Renamed 4 objects" 1
logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
logger -expect log "Renamed 2 objects" 1
debug autoname
logger -check-expected