From fb021b1a6b98382ba17a2ee90cc228073337ceef Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 29 May 2026 18:16:58 +0200
Subject: [PATCH] opt_expr: more patcher again

---
 passes/opt/opt_expr.cc | 28 +++++++---------------------
 1 file changed, 7 insertions(+), 21 deletions(-)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 60ce6a77f..88b730abf 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -649,7 +649,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 					if (sig_b == State::S0) {
 						SigSpec sig_y = sig_a;
 						sig_y.append(RTLIL::Const(State::S0, width-1));
-						// replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_y);
 						patcher.patch(cell, ID::Y, sig_y, "xor_buffer");
 					} else {
 						SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_ID, sig_a) : patcher.Not(NEW_ID, sig_a);
@@ -658,29 +657,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 					}
 					goto next_cell;
 				}
-				// if (cell->type.in(ID($xnor), ID($_XNOR_))) {
-				// 	if (sig_b == State::S1) {
-				// 		SigSpec sig_y = sig_a;
-				// 		sig_y.append(RTLIL::Const(State::S1, width-1));
-				// 		patcher.patch(cell, ID::Y, sig_y, "xnor_buffer");
-				// 	} else {
-				// 		SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_ID, sig_a) : patcher.Not(NEW_ID, sig_a);
-				// 		sig_y.append(RTLIL::Const(State::S1, width-1));
-				// 		patcher.patch(cell, ID::Y, sig_y, "xnor_buffer");
-				// 	}
-				// 	goto next_cell;
-				// }
 				if (cell->type.in(ID($xnor), ID($_XNOR_))) {
-					SigSpec sig_y;
-					if (cell->type == ID($xnor)) {
-						sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit());
-						int width = cell->getParam(ID::Y_WIDTH).as_int();
+					if (sig_b == State::S1) {
+						SigSpec sig_y = sig_a;
 						sig_y.append(RTLIL::Const(State::S1, width-1));
+						patcher.patch(cell, ID::Y, sig_y, "xnor_buffer");
+					} else {
+						SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_ID, sig_a) : patcher.Not(NEW_ID, sig_a);
+						sig_y.append(RTLIL::Const(State::S1, width-1));
+						patcher.patch(cell, ID::Y, sig_y, "xnor_buffer");
 					}
-					else if (cell->type == ID($_XNOR_))
-						sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a));
-					else log_abort();
-					replace_cell(assign_map, module, cell, "xnor_buffer", ID::Y, sig_y);
 					goto next_cell;
 				}
 				log_abort();