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Create clk outside of latch loop

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This commit is contained in:
Eddie Hung 2019-02-08 08:08:49 -08:00
parent 02f603ac1a
commit fafa972238
1 changed files with 9 additions and 7 deletions
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16
frontends/aiger/aigerparse.cc
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@ -116,6 +116,15 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
// Parse latches // Parse latches
std::vector<RTLIL::Wire*> latches; std::vector<RTLIL::Wire*> latches;
RTLIL::Wire *clk_wire = nullptr;
if (L > 0) {
RTLIL::IdString clk_id = RTLIL::escape_id(clk_name.c_str());
clk_wire = module->wire(clk_id);
log_assert(!clk_wire);
log_debug("Creating %s\n", clk_id.c_str());
clk_wire = module->addWire(clk_id);
clk_wire->port_input = true;
}
for (int i = 0; i < L; ++i, ++line_count) { for (int i = 0; i < L; ++i, ++line_count) {
if (!(f >> l1 >> l2)) if (!(f >> l1 >> l2))
log_error("Line %d cannot be interpreted as a latch!\n", line_count); log_error("Line %d cannot be interpreted as a latch!\n", line_count);
@ -123,13 +132,6 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted? log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted?
RTLIL::Wire *q_wire = createWireIfNotExists(l1); RTLIL::Wire *q_wire = createWireIfNotExists(l1);
RTLIL::Wire *d_wire = createWireIfNotExists(l2); RTLIL::Wire *d_wire = createWireIfNotExists(l2);
RTLIL::IdString clk_id = RTLIL::escape_id(clk_name.c_str());
RTLIL::Wire *clk_wire = module->wire(clk_id);
if (!clk_wire) {
log_debug("Creating %s\n", clk_id.c_str());
clk_wire = module->addWire(clk_id);
clk_wire->port_input = true;
}
module->addDff(NEW_ID, clk_wire, d_wire, q_wire); module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
// AIGER latches are assumed to be initialized to zero // AIGER latches are assumed to be initialized to zero