Docs: example_synth fifo update

More detail on `memory_libmap`, the `$__ICE40_RAM4K_` intermediate step, and the
bizarre opt output.

docs/source/code_examples/fifo/fifo.libmap

@@ -0,0 +1,65 @@
+
+yosys> debug memory_libmap -lib +/ice40/brams.txt -lib +/ice40/spram.txt -no-auto-huge
+
+yosys> memory_libmap -lib +/ice40/brams.txt -lib +/ice40/spram.txt -no-auto-huge
+
+4. Executing MEMORY_LIBMAP pass (mapping memories to cells).
+Memory fifo.data mapping candidates (post-geometry):
+- logic fallback
+  - cost: 2048.000000
+- $__ICE40_RAM4K_:
+  - option HAS_BE 0
+  - emulation score: 7
+  - replicates (for ports): 1
+  - replicates (for data): 1
+  - mux score: 0
+  - demux score: 0
+  - cost: 78.000000
+  - abits 11 dbits 2 4 8 16
+  - chosen base width 8
+  - swizzle 0 1 2 3 4 5 6 7
+  - emulate read-first behavior
+  - write port 0: port group W
+    - widths 2 4 8
+  - read port 0: port group R
+    - widths 2 4 8 16
+    - emulate transparency with write port 0
+- $__ICE40_RAM4K_:
+  - option HAS_BE 1
+  - emulation score: 7
+  - replicates (for ports): 1
+  - replicates (for data): 1
+  - mux score: 0
+  - demux score: 0
+  - cost: 78.000000
+  - abits 11 dbits 2 4 8 16
+  - byte width 1
+  - chosen base width 8
+  - swizzle 0 1 2 3 4 5 6 7
+  - emulate read-first behavior
+  - write port 0: port group W
+    - widths 16
+  - read port 0: port group R
+    - widths 2 4 8 16
+    - emulate transparency with write port 0
+Memory fifo.data mapping candidates (after post-geometry prune):
+- logic fallback
+  - cost: 2048.000000
+- $__ICE40_RAM4K_:
+  - option HAS_BE 0
+  - emulation score: 7
+  - replicates (for ports): 1
+  - replicates (for data): 1
+  - mux score: 0
+  - demux score: 0
+  - cost: 78.000000
+  - abits 11 dbits 2 4 8 16
+  - chosen base width 8
+  - swizzle 0 1 2 3 4 5 6 7
+  - emulate read-first behavior
+  - write port 0: port group W
+    - widths 2 4 8
+  - read port 0: port group R
+    - widths 2 4 8 16
+    - emulate transparency with write port 0
+mapping memory fifo.data via $__ICE40_RAM4K_

docs/source/code_examples/fifo/fifo.stat

@@ -36,7 +36,7 @@ yosys> stat
 
 yosys> stat -top fifo
 
-16. Printing statistics.
+17. Printing statistics.
 
 === fifo ===
 

docs/source/code_examples/fifo/fifo_map.ys

@@ -7,11 +7,14 @@ synth_ice40 -top fifo -run begin:map_ram
 
 # ========================================================
 
+echo on
+tee -o fifo.libmap debug memory_libmap -lib +/ice40/brams.txt -lib +/ice40/spram.txt -no-auto-huge
+echo off
 synth_ice40 -top fifo -run map_ram:map_ffram
 select -set mem t:SB_RAM40_4K
 select -set remap @mem %ci:+SB_RAM40_4K[RADDR] @mem %co %%
 select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
-show -color maroon3 @mem -color cornflowerblue @remap -notitle -format dot -prefix rdata_map_ram @rdata_path
+show -color cornflowerblue @remap -notitle -format dot -prefix rdata_map_ram @rdata_path
 
 # ========================================================