From 4c3f517425d7aa7a4349696cd1c21d46aa9ad03f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Dec 2019 16:11:42 -0800 Subject: [PATCH 1/2] Remove delay targets doc --- passes/techmap/abc9.cc | 9 --------- 1 file changed, 9 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index a0403535b..b63a1aa6c 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -825,15 +825,6 @@ struct Abc9Pass : public Pass { log("design as an XAIGER file with write_xaiger and then load that into ABC externally\n"); log("if you want to use ABC to convert your design into another format.\n"); log("\n"); - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("Delay targets can also be specified on a per clock basis by attaching a\n"); - log("'(* abc9_period = *)' attribute onto clock wires (specifically, onto wires\n"); - log("that appear inside any special '$abc9_clock' wires inserted by abc9_map.v). This\n"); - log("can be achieved by modifying the source directly, or through a `setattr`\n"); - log("invocation. Since such attributes cannot yet be propagated through a\n"); - log("hierarchical design (whether or not it has been uniquified) it is recommended\n"); - log("that the design be flattened when using this feature.\n"); - log("\n"); log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n"); log("\n"); } From 0c4be94a02a70de495343258ecda19eb20b3616b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Dec 2019 20:13:25 -0800 Subject: [PATCH 2/2] Add -D DFF_MODE to abc9_map test --- tests/arch/xilinx/abc9_map.ys | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/arch/xilinx/abc9_map.ys b/tests/arch/xilinx/abc9_map.ys index 6823589f1..4a7b9384a 100644 --- a/tests/arch/xilinx/abc9_map.ys +++ b/tests/arch/xilinx/abc9_map.ys @@ -6,7 +6,7 @@ endmodule EOT design -save gold -techmap -map +/xilinx/abc9_map.v -max_iter 1 +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE techmap -map +/xilinx/abc9_unmap.v select -assert-count 1 t:FDSE select -assert-count 1 t:FDSE_1 @@ -29,7 +29,7 @@ endmodule EOT design -save gold -techmap -map +/xilinx/abc9_map.v -max_iter 1 +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE techmap -map +/xilinx/abc9_unmap.v select -assert-count 1 t:FDRE select -assert-count 1 t:FDRE_1 @@ -52,7 +52,7 @@ endmodule EOT design -save gold -techmap -map +/xilinx/abc9_map.v -max_iter 1 +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE techmap -map +/xilinx/abc9_unmap.v select -assert-count 1 t:FDCE select -assert-count 1 t:FDCE_1 @@ -76,7 +76,7 @@ endmodule EOT design -save gold -techmap -map +/xilinx/abc9_map.v -max_iter 1 +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE techmap -map +/xilinx/abc9_unmap.v select -assert-count 1 t:FDPE techmap -autoproc -map +/xilinx/cells_sim.v