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Add test for abc9+mince issue

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2020-03-20 20:35:28 +00:00
parent e813624f21
commit fa77fb857b
1 changed files with 17 additions and 0 deletions
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tests/various/ice40_mince_abc9.ys Normal file
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read_verilog <<EOT
module top(input clk, ce, input [2:0] a, b, output reg [2:0] q);
reg [2:0] aa, bb;
always @(posedge clk) begin
if (ce) begin
aa <= a;
end
bb <= b;
q <= aa + bb;
end
endmodule
EOT
synth_ice40 -abc9 -dffe_min_ce_use 4