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Merge branch 'YosysHQ:main' into main

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Akash Levy 2024-11-08 14:10:24 -08:00 • committed by GitHub
commit fa50434708
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31 changed files with 49 additions and 71 deletions
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2
tests/opt/bug2920.ys
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@ -1,4 +1,4 @@
read_ilang <<EOT
read_rtlil <<EOT
module \mod
wire input 1 \clk

2
tests/opt/memory_bmux2rom.ys
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@ -1,4 +1,4 @@
read_ilang << EOT
read_rtlil << EOT
module \top
wire width 4 input 0 \S

2
tests/opt/opt_lut_elim.ys
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@ -1,3 +1,3 @@
read_ilang opt_lut_elim.il
read_rtlil opt_lut_elim.il
opt_lut
select -assert-count 0 t:$lut

2
tests/opt/opt_lut_ins.ys
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@ -1,4 +1,4 @@
read_ilang << EOF
read_rtlil << EOF
module \top

2
tests/opt/opt_lut_port.ys
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@ -1,3 +1,3 @@
read_ilang opt_lut_port.il
read_rtlil opt_lut_port.il
opt_lut
select -assert-count 2 t:$lut

10
tests/opt/opt_reduce_bmux.ys
View file

@ -1,4 +1,4 @@
read_ilang << EOT
read_rtlil << EOT
module \top
wire width 12 input 0 \A
@ -22,7 +22,7 @@ select -assert-count 1 t:$bmux r:WIDTH=4 %i
design -reset
read_ilang << EOT
read_rtlil << EOT
module \top
wire width 6 input 0 \A
@ -46,7 +46,7 @@ select -assert-count 0 t:$bmux
design -reset
read_ilang << EOT
read_rtlil << EOT
module \top
wire width 160 input 0 \A
@ -70,7 +70,7 @@ select -assert-count 1 t:$bmux r:S_WIDTH=2 %i
design -reset
read_ilang << EOT
read_rtlil << EOT
module \top
wire width 10 input 0 \A
@ -95,7 +95,7 @@ select -assert-count 1 t:$mux
design -reset
read_ilang << EOT
read_rtlil << EOT
module \top
wire width 5 input 0 \A

8
tests/opt/opt_reduce_demux.ys
View file

@ -1,4 +1,4 @@
read_ilang << EOT
read_rtlil << EOT
module \top
wire width 4 input 0 \A
@ -22,7 +22,7 @@ select -assert-count 1 t:$demux r:WIDTH=4 %i
design -reset
read_ilang << EOT
read_rtlil << EOT
module \top
wire width 2 input 1 \S
@ -45,7 +45,7 @@ select -assert-count 0 t:$demux
design -reset
read_ilang << EOT
read_rtlil << EOT
module \top
wire width 5 input 0 \A
@ -69,7 +69,7 @@ select -assert-count 1 t:$demux r:S_WIDTH=2 %i
design -reset
read_ilang << EOT
read_rtlil << EOT
module \top
wire width 5 input 0 \A