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ecp5: Compatibility with Migen AsyncResetSynchronizer

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Signed-off-by: David Shah <davey1576@gmail.com>
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David Shah 2019-02-19 19:35:10 +00:00 • committed by David Shah
parent bb56cb738d
commit fa2f595cfa
2 changed files with 20 additions and 0 deletions
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17
techlibs/ecp5/cells_sim.v
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@ -556,3 +556,20 @@ module DP16KD(
parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
endmodule
// For Diamond compatibility, FIXME: add all Diamond flipflop mappings
module FD1S3BX(input PD, D, CK, output Q);
TRELLIS_FF #(
.GSR("DISABLED"),
.CEMUX("1"),
.CLKMUX("CLK"),
.LSRMUX("LSR"),
.REGSET("SET"),
.SRMODE("ASYNC")
) tff_i (
.CLK(CK),
.LSR(PD),
.DI(D),
.Q(Q)
);
endmodule