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Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
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parent
d4b0f28881
commit
fa295a4528
5 changed files with 39 additions and 37 deletions
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@ -464,7 +464,7 @@ struct EvalPass : public Pass {
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for (auto &it : sets) {
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RTLIL::SigSpec lhs, rhs;
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if (!RTLIL::SigSpec::parse(lhs, module, it.first))
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if (!RTLIL::SigSpec::parse_sel(lhs, design, module, it.first))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", it.first.c_str());
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if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, it.second))
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log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second.c_str());
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@ -486,7 +486,7 @@ struct EvalPass : public Pass {
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{
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for (auto &it : shows) {
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RTLIL::SigSpec signal, value, undef;
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if (!RTLIL::SigSpec::parse(signal, module, it))
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if (!RTLIL::SigSpec::parse_sel(signal, design, module, it))
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log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str());
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signal.optimize();
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value = signal;
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@ -513,14 +513,14 @@ struct EvalPass : public Pass {
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for (auto &it : shows) {
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RTLIL::SigSpec sig;
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if (!RTLIL::SigSpec::parse(sig, module, it))
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if (!RTLIL::SigSpec::parse_sel(sig, design, module, it))
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log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str());
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signal.append(sig);
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}
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for (auto &it : tables) {
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RTLIL::SigSpec sig;
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if (!RTLIL::SigSpec::parse(sig, module, it))
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if (!RTLIL::SigSpec::parse_sel(sig, design, module, it))
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log_cmd_error("Failed to parse table expression `%s'.\n", it.c_str());
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tabsigs.append(sig);
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}
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