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Added generic RTLIL::SigSpec::parse_sel() with support for selection variables

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This commit is contained in:
Clifford Wolf 2014-02-06 19:22:46 +01:00
parent d4b0f28881
commit fa295a4528
5 changed files with 39 additions and 37 deletions
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18
kernel/rtlil.cc
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@ -1649,6 +1649,24 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
return true;
}
bool RTLIL::SigSpec::parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str)
{
if (str.empty() || str[0] != '@')
return parse(sig, module, str);
str = RTLIL::escape_id(str.substr(1));
if (design->selection_vars.count(str) == 0)
return false;
sig = RTLIL::SigSpec();
RTLIL::Selection &sel = design->selection_vars.at(str);
for (auto &it : module->wires)
if (sel.selected_member(module->name, it.first))
sig.append(it.second);
return true;
}
bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
{
if (str == "0") {