3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-22 19:17:55 +00:00

Split sim models into multiple files and implement few

This commit is contained in:
Miodrag Milanovic 2024-05-10 11:15:56 +02:00
parent 04d3672121
commit f9f68c3cd1
8 changed files with 84 additions and 83 deletions

View file

@ -1,14 +1,3 @@
(* blackbox *)
module NX_GCK_U(SI1, SI2, CMD, SO);
input CMD;
input SI1;
input SI2;
output SO;
parameter inv_in = 1'b0;
parameter inv_out = 1'b0;
parameter std_mode = "BYPASS";
endmodule
(* blackbox *)
module NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BSRSTI, BDRSTI, BSRSTO
, BDRSTO, BI1, BI2, BI3, BI4, BI5, BI6, BO1, BO2, BO3, BO4, BO5, BO6, CSRSTI, CDRSTI, CSRSTO, CDRSTO, CI1, CI2, CI3, CI4