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ast: add PRIORITY to $print cells

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Charlotte 2023-06-28 11:51:31 +10:00 committed by Marcelina Kościelnicka
parent 4ffdee65e0
commit f9d38253c5
4 changed files with 12 additions and 2 deletions
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6
docs/source/CHAPTER_CellLib.rst
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@ -644,7 +644,7 @@ has the following parameters:
True if triggered on specific signals defined in ``\TRG``; false if True if triggered on specific signals defined in ``\TRG``; false if
triggered whenever ``\ARGS`` or ``\EN`` change and ``\EN`` is 1. triggered whenever ``\ARGS`` or ``\EN`` change and ``\EN`` is 1.
If ``\TRG_ENABLE`` is true, the following parameters are also set: If ``\TRG_ENABLE`` is true, the following parameters also apply:
``\TRG_WIDTH`` ``\TRG_WIDTH``
The number of bits in the ``\TRG`` port. The number of bits in the ``\TRG`` port.
@ -653,6 +653,10 @@ If ``\TRG_ENABLE`` is true, the following parameters are also set:
For each bit in ``\TRG``, 1 if that signal is positive-edge triggered, 0 if For each bit in ``\TRG``, 1 if that signal is positive-edge triggered, 0 if
negative-edge triggered. negative-edge triggered.
``\PRIORITY``
When multiple ``$print`` cells fire on the same trigger, they execute in
descending priority order.
Ports: Ports:
``\TRG`` ``\TRG``

6
frontends/ast/genrtlil.cc
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@ -315,7 +315,10 @@ struct AST_INTERNAL::ProcessGenerator
// Buffer for generating the init action // Buffer for generating the init action
RTLIL::SigSpec init_lvalue, init_rvalue; RTLIL::SigSpec init_lvalue, init_rvalue;
ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg) // The most recently assigned $print cell \PRIORITY.
int last_print_priority;
ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg), last_print_priority(0)
{ {
// rewrite lookahead references // rewrite lookahead references
LookaheadRewriter la_rewriter(always); LookaheadRewriter la_rewriter(always);
@ -716,6 +719,7 @@ struct AST_INTERNAL::ProcessGenerator
cell->parameters[ID::TRG_WIDTH] = triggers.size(); cell->parameters[ID::TRG_WIDTH] = triggers.size();
cell->parameters[ID::TRG_ENABLE] = !triggers.empty(); cell->parameters[ID::TRG_ENABLE] = !triggers.empty();
cell->parameters[ID::TRG_POLARITY] = polarity; cell->parameters[ID::TRG_POLARITY] = polarity;
cell->parameters[ID::PRIORITY] = --last_print_priority;
cell->setPort(ID::TRG, triggers); cell->setPort(ID::TRG, triggers);
Wire *wire = current_module->addWire(sstr.str() + "_EN", 1); Wire *wire = current_module->addWire(sstr.str() + "_EN", 1);

1
kernel/rtlil.cc
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@ -1724,6 +1724,7 @@ namespace {
param(ID(FORMAT)); param(ID(FORMAT));
param_bool(ID::TRG_ENABLE); param_bool(ID::TRG_ENABLE);
param(ID::TRG_POLARITY); param(ID::TRG_POLARITY);
param(ID::PRIORITY);
port(ID::EN, 1); port(ID::EN, 1);
port(ID::TRG, param(ID::TRG_WIDTH)); port(ID::TRG, param(ID::TRG_WIDTH));
port(ID::ARGS, param(ID::ARGS_WIDTH)); port(ID::ARGS, param(ID::ARGS_WIDTH));

1
techlibs/common/simlib.v
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@ -1805,6 +1805,7 @@ module \$print (EN, TRG, ARGS);
parameter FORMAT = ""; parameter FORMAT = "";
parameter ARGS_WIDTH = 0; parameter ARGS_WIDTH = 0;
parameter PRIORITY = 0;
parameter TRG_ENABLE = 1; parameter TRG_ENABLE = 1;
parameter TRG_WIDTH = 0; parameter TRG_WIDTH = 0;