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https://github.com/YosysHQ/yosys
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Cleanup
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parent
47fd042b9f
commit
f9d08a5e5e
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@ -23,10 +23,10 @@ code sigA clock clock_pol
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sigA = port(mul, \A);
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sigA = port(mul, \A);
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if (ffA) {
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if (ffA) {
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sigA.replace(port(ffA, \Q), port(ffA, \D));
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clock = port(ffA, \CLK).as_bit();
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clock = port(ffA, \CLK).as_bit();
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clock_pol = param(ffA, \CLK_POLARITY).as_bool();
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clock_pol = param(ffA, \CLK_POLARITY).as_bool();
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sigA.replace(port(ffA, \Q), port(ffA, \D));
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}
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}
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endcode
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endcode
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@ -41,8 +41,6 @@ code sigB clock clock_pol
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sigB = port(mul, \B);
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sigB = port(mul, \B);
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if (ffB) {
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if (ffB) {
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sigB.replace(port(ffB, \Q), port(ffB, \D));
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SigBit c = port(ffB, \CLK).as_bit();
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SigBit c = port(ffB, \CLK).as_bit();
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bool cp = param(ffB, \CLK_POLARITY).as_bool();
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bool cp = param(ffB, \CLK_POLARITY).as_bool();
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@ -51,6 +49,8 @@ code sigB clock clock_pol
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clock = c;
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clock = c;
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clock_pol = cp;
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clock_pol = cp;
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sigB.replace(port(ffB, \Q), port(ffB, \D));
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}
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}
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endcode
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endcode
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@ -62,7 +62,7 @@ code sigY sigYused
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for (i = GetSize(sigY); i > 0; i--)
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for (i = GetSize(sigY); i > 0; i--)
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if (nusers(sigY[i-1]) > 1)
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if (nusers(sigY[i-1]) > 1)
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break;
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break;
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sigYused = sigY.extract(0, i).remove_const();
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sigYused = sigY.extract(0, i);
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endcode
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endcode
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match ffY
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match ffY
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