From f9d023c53fedd96ec1b9d3a93d0448291a1f2527 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 9 Sep 2017 10:18:08 +0200
Subject: [PATCH] Add src attribute to extra cells generated by proc_dlatch
---
passes/proc/proc_dlatch.cc | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc
index 6621afd33..15200ec12 100644
--- a/passes/proc/proc_dlatch.cc
+++ b/passes/proc/proc_dlatch.cc
@@ -217,7 +217,7 @@ struct proc_dlatch_db_t
return make_inner(children);
}
- SigBit make_hold(int n)
+ SigBit make_hold(int n, string &src)
{
if (n == true_node)
return State::S1;
@@ -235,20 +235,20 @@ struct proc_dlatch_db_t
if (rule.match == State::S1)
and_bits.append(rule.signal);
else if (rule.match == State::S0)
- and_bits.append(module->Not(NEW_ID, rule.signal));
+ and_bits.append(module->Not(NEW_ID, rule.signal, false, src));
else
- and_bits.append(module->Eq(NEW_ID, rule.signal, rule.match));
+ and_bits.append(module->Eq(NEW_ID, rule.signal, rule.match, false, src));
}
if (!rule.children.empty()) {
SigSpec or_bits;
for (int k : rule.children)
- or_bits.append(make_hold(k));
- and_bits.append(module->ReduceOr(NEW_ID, or_bits));
+ or_bits.append(make_hold(k, src));
+ and_bits.append(module->ReduceOr(NEW_ID, or_bits, false, src));
}
if (GetSize(and_bits) == 2)
- and_bits = module->And(NEW_ID, and_bits[0], and_bits[1]);
+ and_bits = module->And(NEW_ID, and_bits[0], and_bits[1], false, src);
log_assert(GetSize(and_bits) == 1);
rules_sig[n] = and_bits[0];
@@ -340,6 +340,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
RTLIL::SigSig latches_bits, nolatches_bits;
dict<SigBit, SigBit> latches_out_in;
dict<SigBit, int> latches_hold;
+ std::string src = proc->get_src_attribute();
for (auto sr : proc->syncs)
{
@@ -405,7 +406,8 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
SigSpec lhs = latches_bits.first.extract(offset, width);
SigSpec rhs = latches_bits.second.extract(offset, width);
- Cell *cell = db.module->addDlatch(NEW_ID, db.module->Not(NEW_ID, db.make_hold(n)), rhs, lhs);
+ Cell *cell = db.module->addDlatch(NEW_ID, db.module->Not(NEW_ID, db.make_hold(n, src)), rhs, lhs);
+ cell->set_src_attribute(src);
db.generated_dlatches.insert(cell);
log("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n",