From f9c528e981e4afcaba437e793df686a3796ee4a2 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Sun, 2 Nov 2025 11:09:14 +0100 Subject: [PATCH] docs: word_mux grammar --- docs/source/cell/word_mux.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/cell/word_mux.rst b/docs/source/cell/word_mux.rst index 234d1016b..52d1372d3 100644 --- a/docs/source/cell/word_mux.rst +++ b/docs/source/cell/word_mux.rst @@ -16,7 +16,7 @@ value from the ``B`` input is sent to the output. So the `$mux` cell implements the function :verilog:`Y = S ? B : A`. The `$pmux` cell is used to multiplex between many inputs using a one-hot select -signal. Cells of this type have a ``WIDTH`` and a ``S_WIDTH`` parameter and +signal. Cells of this type have a ``WIDTH`` and an ``S_WIDTH`` parameter and inputs ``A``, ``B``, and ``S`` and an output ``Y``. The ``S`` input is ``S_WIDTH`` bits wide. The ``A`` input and the output are both ``WIDTH`` bits wide and the ``B`` input is ``WIDTH*S_WIDTH`` bits wide. When all bits of ``S``