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Merge branch 'master' into xaig

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This commit is contained in:
Eddie Hung 2019-02-19 14:20:04 -08:00
commit f9af902532
9 changed files with 353 additions and 160 deletions
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6
tests/tools/autotest.mk
View file

@ -1,7 +1,7 @@
EXTRA_FLAGS=
SEED=
# Don't bother defining default values for SEED and EXTRA_FLAGS.
# Their "natural" default values should be sufficient,
# and they may be overridden in the environment.
ifneq ($(strip $(SEED)),)
SEEDOPT=-S$(SEED)
endif

42
tests/tools/autotest.sh
View file

@ -17,12 +17,18 @@ scriptfiles=""
scriptopt=""
toolsdir="$(cd $(dirname $0); pwd)"
warn_iverilog_git=false
# The following are used in verilog to firrtl regression tests.
# Typically these will be passed as environment variables:
#EXTRA_FLAGS="--firrtl2verilog 'java -cp /.../firrtl/utils/bin/firrtl.jar firrtl.Driver'"
# The tests are skipped if firrtl2verilog is the empty string (the default).
firrtl2verilog=""
xfirrtl="../xfirrtl"
if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
fi
while getopts xmGl:wkjvref:s:p:n:S:I:B: opt; do
while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do
case "$opt" in
x)
use_xsim=true ;;
@ -61,8 +67,24 @@ while getopts xmGl:wkjvref:s:p:n:S:I:B: opt; do
minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
B)
backend_opts="$backend_opts $OPTARG" ;;
-)
case "${OPTARG}" in
xfirrtl)
xfirrtl="${!OPTIND}"
OPTIND=$(( $OPTIND + 1 ))
;;
firrtl2verilog)
firrtl2verilog="${!OPTIND}"
OPTIND=$(( $OPTIND + 1 ))
;;
*)
if [ "$OPTERR" == 1 ] && [ "${optspec:0:1}" != ":" ]; then
echo "Unknown option --${OPTARG}" >&2
fi
;;
esac;;
*)
echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [-B backend_opt] verilog-files\n" >&2
echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [-B backend_opt] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
exit 1
esac
done
@ -118,6 +140,7 @@ do
"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
frontend="verilog"
fi
rm -f ${bn}_ref.fir
if [ ! -f ../${bn}_tb.v ]; then
"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
@ -157,6 +180,13 @@ do
else
test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
if [ -n "$firrtl2verilog" ]; then
if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v
$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v -X verilog
test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v
fi
fi
fi
touch ../${bn}.log
}
@ -169,14 +199,18 @@ do
( set -ex; body; ) > ${bn}.err 2>&1
fi
did_firrtl=""
if [ -f ${bn}.out/${bn}_ref.fir ]; then
did_firrtl="+FIRRTL "
fi
if [ -f ${bn}.log ]; then
mv ${bn}.err ${bn}.log
echo "${status_prefix}-> ok"
echo "${status_prefix}${did_firrtl}-> ok"
elif [ -f ${bn}.skip ]; then
mv ${bn}.err ${bn}.skip
echo "${status_prefix}-> skip"
else
echo "${status_prefix}-> ERROR!"
echo "${status_prefix}${did_firrtl}-> ERROR!"
if $warn_iverilog_git; then
echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
fi