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Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
This commit is contained in:
Eddie Hung
commit
f9aae90e7a
11 changed files with 198 additions and 156 deletions
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@ -98,7 +98,7 @@ void break_scc(RTLIL::Module *module)
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// its output ports into a new PO, and drive its previous
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// sinks with a new PI
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pool<RTLIL::Const> ids_seen;
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for (auto cell : module->selected_cells()) {
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for (auto cell : module->cells()) {
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auto it = cell->attributes.find(ID(abc9_scc_id));
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if (it == cell->attributes.end())
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continue;
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@ -174,7 +174,7 @@ void prep_dff(RTLIL::Module *module)
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typedef SigSpec clkdomain_t;
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dict<clkdomain_t, int> clk_to_mergeability;
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for (auto cell : module->selected_cells()) {
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for (auto cell : module->cells()) {
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if (cell->type != "$__ABC9_FF_")
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continue;
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@ -202,14 +202,16 @@ void prep_dff(RTLIL::Module *module)
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RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str()));
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if (holes_module) {
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dict<SigSig, SigSig> replace;
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SigMap sigmap(holes_module);
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dict<SigSpec, SigSpec> replace;
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for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
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auto cell = it->second;
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if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
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"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
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SigBit D = cell->getPort("\\D");
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SigBit Q = cell->getPort("\\Q");
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// Remove the DFF cell from what needs to be a combinatorial box
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// Remove the $_DFF_* cell from what needs to be a combinatorial box
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it = holes_module->cells_.erase(it);
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Wire *port;
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if (GetSize(Q.wire) == 1)
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@ -217,10 +219,10 @@ void prep_dff(RTLIL::Module *module)
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else
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port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
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log_assert(port);
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// Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
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// in order to extract the combinatorial control logic that feeds the box
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// Prepare to replace "assign <port> = $_DFF_*.Q;" with "assign <port> = $_DFF_*.D;"
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// in order to extract just the combinatorial control logic that feeds the box
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// (i.e. clock enable, synchronous reset, etc.)
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replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
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replace.insert(std::make_pair(Q,D));
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// Since `flatten` above would have created wires named "<cell>.Q",
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// extract the pre-techmap cell name
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auto pos = Q.wire->name.str().rfind(".");
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@ -228,7 +230,7 @@ void prep_dff(RTLIL::Module *module)
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IdString driver = Q.wire->name.substr(0, pos);
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// And drive the signal that was previously driven by "DFF.Q" (typically
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// used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
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// wire (which itself is driven an input port) we inserted above
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// wire (which itself is driven an by input port) we inserted above
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Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
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log_assert(currQ);
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holes_module->connect(Q, currQ);
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@ -237,11 +239,8 @@ void prep_dff(RTLIL::Module *module)
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++it;
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}
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for (auto &conn : holes_module->connections_) {
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auto it = replace.find(conn);
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if (it != replace.end())
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conn = it->second;
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}
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for (auto &conn : holes_module->connections_)
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conn.second = replace.at(sigmap(conn.second), conn.second);
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}
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}
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@ -256,7 +255,7 @@ void prep_holes(RTLIL::Module *module, bool dff)
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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bool abc9_box_seen = false;
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for (auto cell : module->selected_cells()) {
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for (auto cell : module->cells()) {
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if (cell->type == "$__ABC9_FF_")
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continue;
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@ -294,21 +293,23 @@ void prep_holes(RTLIL::Module *module, bool dff)
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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#if 0
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toposort.analyze_loops = true;
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#endif
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if (ys_debug(1))
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toposort.analyze_loops = true;
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bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
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#if 0
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unsigned i = 0;
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for (auto &it : toposort.loops) {
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log(" loop %d\n", i++);
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for (auto cell_name : it) {
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auto cell = module->cell(cell_name);
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log_assert(cell);
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log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
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if (ys_debug(1)) {
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unsigned i = 0;
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for (auto &it : toposort.loops) {
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log(" loop %d\n", i++);
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for (auto cell_name : it) {
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auto cell = module->cell(cell_name);
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log_assert(cell);
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log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
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}
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}
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}
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#endif
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log_assert(no_loops);
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vector<Cell*> box_list;
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@ -377,100 +378,97 @@ void prep_holes(RTLIL::Module *module, bool dff)
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log_assert(orig_box_module);
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IdString derived_name = orig_box_module->derive(design, cell->parameters);
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RTLIL::Module* box_module = design->module(derived_name);
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cell->type = derived_name;
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cell->parameters.clear();
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//cell->type = derived_name;
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//cell->parameters.clear();
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int box_inputs = 0;
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auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
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Cell *holes_cell = r.first->second;
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if (r.second && box_module->get_bool_attribute("\\whitebox")) {
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holes_cell = holes_module->addCell(cell->name, cell->type);
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holes_cell->parameters = cell->parameters;
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r.first->second = holes_cell;
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if (box_module->has_processes())
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Pass::call_on_module(design, box_module, "proc");
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}
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auto r2 = box_ports.insert(cell->type);
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if (r2.second) {
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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for (const auto &port_name : box_module->ports) {
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auto w = box_module->wire(port_name);
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log_assert(w);
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input)
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carry_in = port_name;
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if (w->port_output)
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carry_out = port_name;
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auto r = cell_cache.insert(derived_name);
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auto &holes_cell = r.first->second;
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if (r.second) {
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auto r2 = box_ports.insert(cell->type);
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if (r2.second) {
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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for (const auto &port_name : box_module->ports) {
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auto w = box_module->wire(port_name);
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log_assert(w);
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input)
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carry_in = port_name;
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if (w->port_output)
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carry_out = port_name;
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}
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else
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r2.first->second.push_back(port_name);
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}
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if (carry_in != IdString()) {
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r2.first->second.push_back(carry_in);
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r2.first->second.push_back(carry_out);
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}
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else
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r2.first->second.push_back(port_name);
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}
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if (carry_in != IdString()) {
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r2.first->second.push_back(carry_in);
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r2.first->second.push_back(carry_out);
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}
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}
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if (box_module->get_bool_attribute("\\whitebox")) {
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holes_cell = holes_module->addCell(cell->name, derived_name);
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for (const auto &port_name : box_ports.at(cell->type)) {
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RTLIL::Wire *w = box_module->wire(port_name);
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log_assert(w);
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RTLIL::Wire *holes_wire;
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RTLIL::SigSpec port_sig;
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if (w->port_input)
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for (int i = 0; i < GetSize(w); i++) {
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if (box_module->has_processes())
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Pass::call_on_module(design, box_module, "proc");
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int box_inputs = 0;
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for (auto port_name : box_ports.at(cell->type)) {
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RTLIL::Wire *w = box_module->wire(port_name);
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log_assert(w);
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log_assert(!w->port_input || !w->port_output);
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auto &conn = holes_cell->connections_[port_name];
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if (w->port_input) {
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for (int i = 0; i < GetSize(w); i++) {
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box_inputs++;
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RTLIL::Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
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if (!holes_wire) {
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holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
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holes_wire->port_input = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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}
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conn.append(holes_wire);
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}
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}
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else if (w->port_output)
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conn = holes_module->addWire(stringf("%s.%s", derived_name.c_str(), log_id(port_name)), GetSize(w));
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}
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// For flops only, create an extra 1-bit input that drives a new wire
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// called "<cell>.abc9_ff.Q" that is used below
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if (box_module->get_bool_attribute("\\abc9_flop")) {
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box_inputs++;
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holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
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Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
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if (!holes_wire) {
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holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
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holes_wire->port_input = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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}
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if (holes_cell)
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port_sig.append(holes_wire);
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Wire *Q = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
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holes_module->connect(Q, holes_wire);
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}
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if (w->port_output)
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for (int i = 0; i < GetSize(w); i++) {
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if (GetSize(w) == 1)
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holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
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else
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holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
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holes_wire->port_output = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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if (holes_cell)
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port_sig.append(holes_wire);
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else
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holes_module->connect(holes_wire, State::S0);
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}
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if (!port_sig.empty()) {
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if (r.second)
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holes_cell->setPort(w->name, port_sig);
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else
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holes_module->connect(holes_cell->getPort(w->name), port_sig);
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}
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else // box_module is a blackbox
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log_assert(holes_cell == nullptr);
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}
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// For flops only, create an extra 1-bit input that drives a new wire
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// called "<cell>.$abc9_currQ" that is used below
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if (box_module->get_bool_attribute("\\abc9_flop")) {
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log_assert(holes_cell);
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box_inputs++;
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Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
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if (!holes_wire) {
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holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
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holes_wire->port_input = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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}
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Wire *w = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
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holes_module->connect(w, holes_wire);
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for (auto port_name : box_ports.at(cell->type)) {
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RTLIL::Wire *w = box_module->wire(port_name);
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log_assert(w);
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if (!w->port_output)
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continue;
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Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(port_name)), GetSize(w));
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holes_wire->port_output = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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if (holes_cell) // whitebox
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holes_module->connect(holes_wire, holes_cell->getPort(port_name));
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else // blackbox
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holes_module->connect(holes_wire, Const(State::S0, GetSize(w)));
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}
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}
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}
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@ -1059,7 +1057,11 @@ struct Abc9OpsPass : public Pass {
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}
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extra_args(args, argidx, design);
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// TODO: Check at least one mode given
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if (!(check_mode || break_scc_mode || unbreak_scc_mode || prep_times_mode || prep_holes_mode || prep_dff_mode || !write_box_src.empty() || reintegrate_mode))
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log_cmd_error("At least one of -check, -{,un}break_scc, -prep_{times,holes,dff}, -write_box, -reintegrate must be specified.\n");
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if (dff_mode && !prep_holes_mode)
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log_cmd_error("'-dff' option is only relevant for -prep_holes.\n");
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if (check_mode)
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check(design);
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@ -1075,6 +1077,9 @@ struct Abc9OpsPass : public Pass {
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continue;
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}
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if (!design->selected_whole_module(mod))
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log_error("Can't handle partially selected module %s!\n", log_id(mod));
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if (break_scc_mode)
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break_scc(mod);
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if (unbreak_scc_mode)
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