mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-19 12:23:39 +00:00
namespace Yosys
This commit is contained in:
parent
bcd2625a82
commit
f9a307a50b
96 changed files with 878 additions and 585 deletions
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@ -22,6 +22,9 @@
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#include <stdlib.h>
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#include <stdio.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct OptPass : public Pass {
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OptPass() : Pass("opt", "perform simple optimizations") { }
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virtual void help()
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@ -142,3 +145,4 @@ struct OptPass : public Pass {
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}
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} OptPass;
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PRIVATE_NAMESPACE_END
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@ -25,12 +25,15 @@
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#include <stdio.h>
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#include <set>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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using RTLIL::id2cstr;
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static CellTypes ct, ct_reg, ct_all;
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static int count_rm_cells, count_rm_wires;
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CellTypes ct, ct_reg, ct_all;
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int count_rm_cells, count_rm_wires;
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static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
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void rmunused_module_cells(RTLIL::Module *module, bool verbose)
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{
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SigMap assign_map(module);
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std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> queue, unused;
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@ -93,7 +96,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
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}
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}
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static int count_nontrivial_wire_attrs(RTLIL::Wire *w)
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int count_nontrivial_wire_attrs(RTLIL::Wire *w)
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{
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int count = w->attributes.size();
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count -= w->attributes.count("\\src");
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@ -101,7 +104,7 @@ static int count_nontrivial_wire_attrs(RTLIL::Wire *w)
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return count;
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}
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static bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPool &conns, std::set<RTLIL::Wire*> &direct_wires)
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bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPool &conns, std::set<RTLIL::Wire*> &direct_wires)
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{
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RTLIL::Wire *w1 = s1.wire;
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RTLIL::Wire *w2 = s2.wire;
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@ -136,7 +139,7 @@ static bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s,
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return w2->name < w1->name;
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}
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static bool check_public_name(RTLIL::IdString id)
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bool check_public_name(RTLIL::IdString id)
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{
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const std::string &id_str = id.str();
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if (id_str[0] == '$')
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@ -148,7 +151,7 @@ static bool check_public_name(RTLIL::IdString id)
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return true;
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}
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static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbose)
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void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbose)
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{
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SigPool register_signals;
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SigPool connected_signals;
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@ -285,7 +288,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
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log(" removed %d unused temporary wires.\n", del_wires_count);
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}
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static void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose)
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void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose)
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{
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if (verbose)
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log("Finding unused cells or wires in module %s..\n", module->name.c_str());
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@ -419,3 +422,4 @@ struct CleanPass : public Pass {
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}
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} CleanPass;
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PRIVATE_NAMESPACE_END
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@ -26,9 +26,12 @@
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#include <stdio.h>
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#include <algorithm>
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static bool did_something;
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
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bool did_something;
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void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
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{
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CellTypes ct(design);
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SigMap sigmap(module);
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@ -70,7 +73,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
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}
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}
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static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
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void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
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{
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RTLIL::SigSpec Y = cell->getPort(out_port);
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out_val.extend_u0(Y.size(), false);
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@ -85,7 +88,7 @@ static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell
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did_something = true;
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}
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static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, SigMap &sigmap)
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bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, SigMap &sigmap)
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{
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std::string b_name = cell->hasPort("\\B") ? "\\B" : "\\A";
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@ -183,7 +186,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
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return true;
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}
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static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc)
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void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc)
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{
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if (!design->selected(module))
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return;
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@ -1006,3 +1009,4 @@ struct OptConstPass : public Pass {
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}
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} OptConstPass;
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PRIVATE_NAMESPACE_END
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@ -25,6 +25,9 @@
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#include <stdio.h>
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#include <set>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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using RTLIL::id2cstr;
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struct OptMuxtreeWorker
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@ -438,3 +441,4 @@ struct OptMuxtreePass : public Pass {
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}
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} OptMuxtreePass;
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PRIVATE_NAMESPACE_END
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#include <stdio.h>
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#include <set>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct OptReduceWorker
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{
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RTLIL::Design *design;
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@ -378,3 +381,4 @@ struct OptReducePass : public Pass {
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}
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} OptReducePass;
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PRIVATE_NAMESPACE_END
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@ -23,10 +23,13 @@
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#include <stdlib.h>
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#include <stdio.h>
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static SigMap assign_map, dff_init_map;
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static SigSet<RTLIL::Cell*> mux_drivers;
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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SigMap assign_map, dff_init_map;
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SigSet<RTLIL::Cell*> mux_drivers;
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bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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{
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RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r;
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RTLIL::Const val_cp, val_rp, val_rv;
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}
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} OptRmdffPass;
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PRIVATE_NAMESPACE_END
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@ -28,6 +28,9 @@
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#define USE_CELL_HASH_CACHE
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct OptShareWorker
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{
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RTLIL::Design *design;
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@ -319,3 +322,4 @@ struct OptSharePass : public Pass {
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}
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} OptSharePass;
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PRIVATE_NAMESPACE_END
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#include "kernel/modtools.h"
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#include "kernel/utils.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct ShareWorkerConfig
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} SharePass;
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PRIVATE_NAMESPACE_END
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