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https://github.com/YosysHQ/yosys
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namespace Yosys
This commit is contained in:
Clifford Wolf
parent
bcd2625a82
commit
f9a307a50b
96 changed files with 878 additions and 585 deletions
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@ -21,145 +21,145 @@
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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namespace
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct statdata_t
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{
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struct statdata_t
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{
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#define STAT_INT_MEMBERS X(num_wires) X(num_wire_bits) X(num_pub_wires) X(num_pub_wire_bits) \
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X(num_memories) X(num_memory_bits) X(num_cells) X(num_processes)
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#define STAT_INT_MEMBERS X(num_wires) X(num_wire_bits) X(num_pub_wires) X(num_pub_wire_bits) \
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X(num_memories) X(num_memory_bits) X(num_cells) X(num_processes)
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#define X(_name) int _name;
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#define X(_name) int _name;
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STAT_INT_MEMBERS
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#undef X
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std::map<RTLIL::IdString, int> num_cells_by_type;
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statdata_t operator+(const statdata_t &other) const
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{
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statdata_t sum = other;
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#define X(_name) sum._name += _name;
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STAT_INT_MEMBERS
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#undef X
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std::map<RTLIL::IdString, int> num_cells_by_type;
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statdata_t operator+(const statdata_t &other) const
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{
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statdata_t sum = other;
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#define X(_name) sum._name += _name;
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STAT_INT_MEMBERS
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#undef X
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for (auto &it : num_cells_by_type)
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sum.num_cells_by_type[it.first] += it.second;
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return sum;
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}
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statdata_t operator*(int other) const
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{
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statdata_t sum = *this;
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#define X(_name) sum._name *= other;
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STAT_INT_MEMBERS
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#undef X
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for (auto &it : sum.num_cells_by_type)
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it.second *= other;
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return sum;
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}
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statdata_t()
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{
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#define X(_name) _name = 0;
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STAT_INT_MEMBERS
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#undef X
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}
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statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode)
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{
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#define X(_name) _name = 0;
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STAT_INT_MEMBERS
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#undef X
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for (auto &it : mod->wires_)
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{
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if (!design->selected(mod, it.second))
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continue;
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if (it.first[0] == '\\') {
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num_pub_wires++;
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num_pub_wire_bits += it.second->width;
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}
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num_wires++;
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num_wire_bits += it.second->width;
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}
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for (auto &it : mod->memories) {
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if (!design->selected(mod, it.second))
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continue;
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num_memories++;
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num_memory_bits += it.second->width * it.second->size;
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}
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for (auto &it : mod->cells_)
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{
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if (!design->selected(mod, it.second))
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continue;
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RTLIL::IdString cell_type = it.second->type;
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if (width_mode)
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{
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if (cell_type.in("$not", "$pos", "$neg",
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"$logic_not", "$logic_and", "$logic_or",
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"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
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"$lut", "$and", "$or", "$xor", "$xnor",
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"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
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"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
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"$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
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int width_a = it.second->hasPort("\\A") ? SIZE(it.second->getPort("\\A")) : 0;
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int width_b = it.second->hasPort("\\B") ? SIZE(it.second->getPort("\\B")) : 0;
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int width_y = it.second->hasPort("\\Y") ? SIZE(it.second->getPort("\\Y")) : 0;
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cell_type = stringf("%s_%d", cell_type.c_str(), std::max<int>({width_a, width_b, width_y}));
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}
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else if (cell_type.in("$mux", "$pmux"))
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cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Y")));
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else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr"))
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cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Q")));
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}
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num_cells++;
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num_cells_by_type[cell_type]++;
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}
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for (auto &it : mod->processes) {
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if (!design->selected(mod, it.second))
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continue;
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num_processes++;
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}
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}
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void log_data()
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{
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log(" Number of wires: %6d\n", num_wires);
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log(" Number of wire bits: %6d\n", num_wire_bits);
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log(" Number of public wires: %6d\n", num_pub_wires);
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log(" Number of public wire bits: %6d\n", num_pub_wire_bits);
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log(" Number of memories: %6d\n", num_memories);
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log(" Number of memory bits: %6d\n", num_memory_bits);
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log(" Number of processes: %6d\n", num_processes);
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log(" Number of cells: %6d\n", num_cells);
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for (auto &it : num_cells_by_type)
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log(" %-26s %6d\n", RTLIL::id2cstr(it.first), it.second);
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}
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};
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statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTLIL::IdString mod, int level)
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{
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statdata_t mod_data = mod_stat.at(mod);
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std::map<RTLIL::IdString, int> num_cells_by_type;
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num_cells_by_type.swap(mod_data.num_cells_by_type);
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#undef X
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for (auto &it : num_cells_by_type)
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if (mod_stat.count(it.first) > 0) {
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log(" %*s%-*s %6d\n", 2*level, "", 26-2*level, RTLIL::id2cstr(it.first), it.second);
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mod_data = mod_data + hierarchy_worker(mod_stat, it.first, level+1) * it.second;
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mod_data.num_cells -= it.second;
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} else {
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mod_data.num_cells_by_type[it.first] += it.second;
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sum.num_cells_by_type[it.first] += it.second;
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return sum;
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}
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statdata_t operator*(int other) const
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{
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statdata_t sum = *this;
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#define X(_name) sum._name *= other;
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STAT_INT_MEMBERS
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#undef X
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for (auto &it : sum.num_cells_by_type)
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it.second *= other;
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return sum;
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}
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statdata_t()
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{
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#define X(_name) _name = 0;
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STAT_INT_MEMBERS
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#undef X
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}
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statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode)
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{
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#define X(_name) _name = 0;
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STAT_INT_MEMBERS
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#undef X
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for (auto &it : mod->wires_)
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{
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if (!design->selected(mod, it.second))
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continue;
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if (it.first[0] == '\\') {
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num_pub_wires++;
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num_pub_wire_bits += it.second->width;
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}
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return mod_data;
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num_wires++;
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num_wire_bits += it.second->width;
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}
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for (auto &it : mod->memories) {
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if (!design->selected(mod, it.second))
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continue;
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num_memories++;
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num_memory_bits += it.second->width * it.second->size;
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}
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for (auto &it : mod->cells_)
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{
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if (!design->selected(mod, it.second))
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continue;
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RTLIL::IdString cell_type = it.second->type;
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if (width_mode)
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{
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if (cell_type.in("$not", "$pos", "$neg",
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"$logic_not", "$logic_and", "$logic_or",
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"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
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"$lut", "$and", "$or", "$xor", "$xnor",
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"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
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"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
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"$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
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int width_a = it.second->hasPort("\\A") ? SIZE(it.second->getPort("\\A")) : 0;
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int width_b = it.second->hasPort("\\B") ? SIZE(it.second->getPort("\\B")) : 0;
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int width_y = it.second->hasPort("\\Y") ? SIZE(it.second->getPort("\\Y")) : 0;
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cell_type = stringf("%s_%d", cell_type.c_str(), std::max<int>({width_a, width_b, width_y}));
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}
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else if (cell_type.in("$mux", "$pmux"))
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cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Y")));
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else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr"))
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cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Q")));
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}
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num_cells++;
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num_cells_by_type[cell_type]++;
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}
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for (auto &it : mod->processes) {
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if (!design->selected(mod, it.second))
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continue;
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num_processes++;
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}
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}
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void log_data()
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{
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log(" Number of wires: %6d\n", num_wires);
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log(" Number of wire bits: %6d\n", num_wire_bits);
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log(" Number of public wires: %6d\n", num_pub_wires);
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log(" Number of public wire bits: %6d\n", num_pub_wire_bits);
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log(" Number of memories: %6d\n", num_memories);
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log(" Number of memory bits: %6d\n", num_memory_bits);
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log(" Number of processes: %6d\n", num_processes);
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log(" Number of cells: %6d\n", num_cells);
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for (auto &it : num_cells_by_type)
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log(" %-26s %6d\n", RTLIL::id2cstr(it.first), it.second);
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}
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};
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statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTLIL::IdString mod, int level)
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{
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statdata_t mod_data = mod_stat.at(mod);
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std::map<RTLIL::IdString, int> num_cells_by_type;
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num_cells_by_type.swap(mod_data.num_cells_by_type);
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for (auto &it : num_cells_by_type)
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if (mod_stat.count(it.first) > 0) {
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log(" %*s%-*s %6d\n", 2*level, "", 26-2*level, RTLIL::id2cstr(it.first), it.second);
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mod_data = mod_data + hierarchy_worker(mod_stat, it.first, level+1) * it.second;
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mod_data.num_cells -= it.second;
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} else {
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mod_data.num_cells_by_type[it.first] += it.second;
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}
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return mod_data;
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}
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struct StatPass : public Pass {
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@ -243,3 +243,4 @@ struct StatPass : public Pass {
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}
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} StatPass;
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PRIVATE_NAMESPACE_END
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