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namespace Yosys

Browse source
This commit is contained in:
Clifford Wolf 2014-09-27 16:17:53 +02:00
parent bcd2625a82
commit f9a307a50b
96 changed files with 878 additions and 585 deletions
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8
passes/cmds/add.cc
View file

@ -17,9 +17,10 @@
*
*/
#include "kernel/register.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
#include "kernel/yosys.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
{
@ -150,3 +151,4 @@ struct AddPass : public Pass {
}
} AddPass;
PRIVATE_NAMESPACE_END

4
passes/cmds/connect.cc
View file

@ -23,6 +23,9 @@
#include "kernel/celltypes.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, RTLIL::SigSpec &sig)
{
CellTypes ct(design);
@ -183,3 +186,4 @@ struct ConnectPass : public Pass {
}
} ConnectPass;
PRIVATE_NAMESPACE_END

4
passes/cmds/connwrappers.cc
View file

@ -22,6 +22,9 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct ConnwrappersWorker
{
struct portdecl_t {
@ -203,3 +206,4 @@ struct ConnwrappersPass : public Pass {
}
} ConnwrappersPass;
PRIVATE_NAMESPACE_END

4
passes/cmds/copy.cc
View file

@ -21,6 +21,9 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct CopyPass : public Pass {
CopyPass() : Pass("copy", "copy modules in the design") { }
virtual void help()
@ -53,3 +56,4 @@ struct CopyPass : public Pass {
}
} CopyPass;
PRIVATE_NAMESPACE_END

4
passes/cmds/cover.cc
View file

@ -25,6 +25,9 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct CoverPass : public Pass {
CoverPass() : Pass("cover", "print code coverage counters") { }
virtual void help()
@ -142,3 +145,4 @@ struct CoverPass : public Pass {
}
} CoverPass;
PRIVATE_NAMESPACE_END

8
passes/cmds/delete.cc
View file

@ -17,9 +17,10 @@
*
*/
#include "kernel/register.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
#include "kernel/yosys.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct DeletePass : public Pass {
DeletePass() : Pass("delete", "delete objects in the design") { }
@ -140,3 +141,4 @@ struct DeletePass : public Pass {
}
} DeletePass;
PRIVATE_NAMESPACE_END

4
passes/cmds/log.cc
View file

@ -22,6 +22,9 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct LogPass : public Pass {
LogPass() : Pass("log", "print text and log files") { }
virtual void help()
@ -76,3 +79,4 @@ struct LogPass : public Pass {
}
} LogPass;
PRIVATE_NAMESPACE_END

4
passes/cmds/rename.cc
View file

@ -21,6 +21,9 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
static void rename_in_module(RTLIL::Module *module, std::string from_name, std::string to_name)
{
from_name = RTLIL::escape_id(from_name);
@ -196,3 +199,4 @@ struct RenamePass : public Pass {
}
} RenamePass;
PRIVATE_NAMESPACE_END

4
passes/cmds/scatter.cc
View file

@ -22,6 +22,9 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct ScatterPass : public Pass {
ScatterPass() : Pass("scatter", "add additional intermediate nets") { }
virtual void help()
@ -67,3 +70,4 @@ struct ScatterPass : public Pass {
}
} ScatterPass;
PRIVATE_NAMESPACE_END

4
passes/cmds/scc.cc
View file

@ -29,6 +29,9 @@
#include <stdio.h>
#include <set>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SccWorker
{
RTLIL::Design *design;
@ -297,3 +300,4 @@ struct SccPass : public Pass {
}
} SccPass;
PRIVATE_NAMESPACE_END

10
passes/cmds/select.cc
View file

@ -25,6 +25,9 @@
#include <fnmatch.h>
#include <errno.h>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
using RTLIL::id2cstr;
static std::vector<RTLIL::Selection> work_stack;
@ -795,6 +798,9 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
select_filter_active_mod(design, work_stack.back());
}
PRIVATE_NAMESPACE_END
YOSYS_NAMESPACE_BEGIN
// used in kernel/register.cc and maybe other locations, extern decl. in register.h
void handle_extra_select_args(Pass *pass, std::vector<std::string> args, size_t argidx, size_t args_size, RTLIL::Design *design)
{
@ -818,6 +824,9 @@ void handle_extra_select_args(Pass *pass, std::vector<std::string> args, size_t
design->selection_stack.push_back(RTLIL::Selection(false));
}
YOSYS_NAMESPACE_END
PRIVATE_NAMESPACE_BEGIN
struct SelectPass : public Pass {
SelectPass() : Pass("select", "modify and view the list of selected objects") { }
virtual void help()
@ -1384,3 +1393,4 @@ struct LsPass : public Pass {
}
} LsPass;
PRIVATE_NAMESPACE_END

4
passes/cmds/setattr.cc
View file

@ -21,6 +21,9 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct setunset_t
{
RTLIL::IdString name;
@ -178,3 +181,4 @@ struct SetparamPass : public Pass {
}
} SetparamPass;
PRIVATE_NAMESPACE_END

4
passes/cmds/setundef.cc
View file

@ -23,6 +23,9 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SetundefWorker
{
int next_bit_mode;
@ -153,3 +156,4 @@ struct SetundefPass : public Pass {
}
} SetundefPass;
PRIVATE_NAMESPACE_END

4
passes/cmds/show.cc
View file

@ -27,6 +27,9 @@
# include <readline/readline.h>
#endif
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
using RTLIL::id2cstr;
#undef CLUSTER_CELLS_AND_PORTBOXES
@ -795,3 +798,4 @@ struct ShowPass : public Pass {
}
} ShowPass;
PRIVATE_NAMESPACE_END

4
passes/cmds/splice.cc
View file

@ -24,6 +24,9 @@
#include "kernel/log.h"
#include <tuple>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SpliceWorker
{
RTLIL::Design *design;
@ -349,3 +352,4 @@ struct SplicePass : public Pass {
}
} SplicePass;
PRIVATE_NAMESPACE_END

4
passes/cmds/splitnets.cc
View file

@ -22,6 +22,9 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SplitnetsWorker
{
std::map<RTLIL::Wire*, std::vector<RTLIL::SigBit>> splitmap;
@ -183,3 +186,4 @@ struct SplitnetsPass : public Pass {
}
} SplitnetsPass;
PRIVATE_NAMESPACE_END

265
passes/cmds/stat.cc
View file

@ -21,145 +21,145 @@
#include "kernel/celltypes.h"
#include "kernel/log.h"
namespace
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct statdata_t
{
struct statdata_t
{
#define STAT_INT_MEMBERS X(num_wires) X(num_wire_bits) X(num_pub_wires) X(num_pub_wire_bits) \
X(num_memories) X(num_memory_bits) X(num_cells) X(num_processes)
#define STAT_INT_MEMBERS X(num_wires) X(num_wire_bits) X(num_pub_wires) X(num_pub_wire_bits) \
X(num_memories) X(num_memory_bits) X(num_cells) X(num_processes)
#define X(_name) int _name;
#define X(_name) int _name;
STAT_INT_MEMBERS
#undef X
std::map<RTLIL::IdString, int> num_cells_by_type;
statdata_t operator+(const statdata_t &other) const
{
statdata_t sum = other;
#define X(_name) sum._name += _name;
STAT_INT_MEMBERS
#undef X
std::map<RTLIL::IdString, int> num_cells_by_type;
statdata_t operator+(const statdata_t &other) const
{
statdata_t sum = other;
#define X(_name) sum._name += _name;
STAT_INT_MEMBERS
#undef X
for (auto &it : num_cells_by_type)
sum.num_cells_by_type[it.first] += it.second;
return sum;
}
statdata_t operator*(int other) const
{
statdata_t sum = *this;
#define X(_name) sum._name *= other;
STAT_INT_MEMBERS
#undef X
for (auto &it : sum.num_cells_by_type)
it.second *= other;
return sum;
}
statdata_t()
{
#define X(_name) _name = 0;
STAT_INT_MEMBERS
#undef X
}
statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode)
{
#define X(_name) _name = 0;
STAT_INT_MEMBERS
#undef X
for (auto &it : mod->wires_)
{
if (!design->selected(mod, it.second))
continue;
if (it.first[0] == '\\') {
num_pub_wires++;
num_pub_wire_bits += it.second->width;
}
num_wires++;
num_wire_bits += it.second->width;
}
for (auto &it : mod->memories) {
if (!design->selected(mod, it.second))
continue;
num_memories++;
num_memory_bits += it.second->width * it.second->size;
}
for (auto &it : mod->cells_)
{
if (!design->selected(mod, it.second))
continue;
RTLIL::IdString cell_type = it.second->type;
if (width_mode)
{
if (cell_type.in("$not", "$pos", "$neg",
"$logic_not", "$logic_and", "$logic_or",
"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
"$lut", "$and", "$or", "$xor", "$xnor",
"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
"$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
int width_a = it.second->hasPort("\\A") ? SIZE(it.second->getPort("\\A")) : 0;
int width_b = it.second->hasPort("\\B") ? SIZE(it.second->getPort("\\B")) : 0;
int width_y = it.second->hasPort("\\Y") ? SIZE(it.second->getPort("\\Y")) : 0;
cell_type = stringf("%s_%d", cell_type.c_str(), std::max<int>({width_a, width_b, width_y}));
}
else if (cell_type.in("$mux", "$pmux"))
cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Y")));
else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr"))
cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Q")));
}
num_cells++;
num_cells_by_type[cell_type]++;
}
for (auto &it : mod->processes) {
if (!design->selected(mod, it.second))
continue;
num_processes++;
}
}
void log_data()
{
log(" Number of wires: %6d\n", num_wires);
log(" Number of wire bits: %6d\n", num_wire_bits);
log(" Number of public wires: %6d\n", num_pub_wires);
log(" Number of public wire bits: %6d\n", num_pub_wire_bits);
log(" Number of memories: %6d\n", num_memories);
log(" Number of memory bits: %6d\n", num_memory_bits);
log(" Number of processes: %6d\n", num_processes);
log(" Number of cells: %6d\n", num_cells);
for (auto &it : num_cells_by_type)
log(" %-26s %6d\n", RTLIL::id2cstr(it.first), it.second);
}
};
statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTLIL::IdString mod, int level)
{
statdata_t mod_data = mod_stat.at(mod);
std::map<RTLIL::IdString, int> num_cells_by_type;
num_cells_by_type.swap(mod_data.num_cells_by_type);
#undef X
for (auto &it : num_cells_by_type)
if (mod_stat.count(it.first) > 0) {
log(" %*s%-*s %6d\n", 2*level, "", 26-2*level, RTLIL::id2cstr(it.first), it.second);
mod_data = mod_data + hierarchy_worker(mod_stat, it.first, level+1) * it.second;
mod_data.num_cells -= it.second;
} else {
mod_data.num_cells_by_type[it.first] += it.second;
sum.num_cells_by_type[it.first] += it.second;
return sum;
}
statdata_t operator*(int other) const
{
statdata_t sum = *this;
#define X(_name) sum._name *= other;
STAT_INT_MEMBERS
#undef X
for (auto &it : sum.num_cells_by_type)
it.second *= other;
return sum;
}
statdata_t()
{
#define X(_name) _name = 0;
STAT_INT_MEMBERS
#undef X
}
statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode)
{
#define X(_name) _name = 0;
STAT_INT_MEMBERS
#undef X
for (auto &it : mod->wires_)
{
if (!design->selected(mod, it.second))
continue;
if (it.first[0] == '\\') {
num_pub_wires++;
num_pub_wire_bits += it.second->width;
}
return mod_data;
num_wires++;
num_wire_bits += it.second->width;
}
for (auto &it : mod->memories) {
if (!design->selected(mod, it.second))
continue;
num_memories++;
num_memory_bits += it.second->width * it.second->size;
}
for (auto &it : mod->cells_)
{
if (!design->selected(mod, it.second))
continue;
RTLIL::IdString cell_type = it.second->type;
if (width_mode)
{
if (cell_type.in("$not", "$pos", "$neg",
"$logic_not", "$logic_and", "$logic_or",
"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
"$lut", "$and", "$or", "$xor", "$xnor",
"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
"$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
int width_a = it.second->hasPort("\\A") ? SIZE(it.second->getPort("\\A")) : 0;
int width_b = it.second->hasPort("\\B") ? SIZE(it.second->getPort("\\B")) : 0;
int width_y = it.second->hasPort("\\Y") ? SIZE(it.second->getPort("\\Y")) : 0;
cell_type = stringf("%s_%d", cell_type.c_str(), std::max<int>({width_a, width_b, width_y}));
}
else if (cell_type.in("$mux", "$pmux"))
cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Y")));
else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr"))
cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Q")));
}
num_cells++;
num_cells_by_type[cell_type]++;
}
for (auto &it : mod->processes) {
if (!design->selected(mod, it.second))
continue;
num_processes++;
}
}
void log_data()
{
log(" Number of wires: %6d\n", num_wires);
log(" Number of wire bits: %6d\n", num_wire_bits);
log(" Number of public wires: %6d\n", num_pub_wires);
log(" Number of public wire bits: %6d\n", num_pub_wire_bits);
log(" Number of memories: %6d\n", num_memories);
log(" Number of memory bits: %6d\n", num_memory_bits);
log(" Number of processes: %6d\n", num_processes);
log(" Number of cells: %6d\n", num_cells);
for (auto &it : num_cells_by_type)
log(" %-26s %6d\n", RTLIL::id2cstr(it.first), it.second);
}
};
statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTLIL::IdString mod, int level)
{
statdata_t mod_data = mod_stat.at(mod);
std::map<RTLIL::IdString, int> num_cells_by_type;
num_cells_by_type.swap(mod_data.num_cells_by_type);
for (auto &it : num_cells_by_type)
if (mod_stat.count(it.first) > 0) {
log(" %*s%-*s %6d\n", 2*level, "", 26-2*level, RTLIL::id2cstr(it.first), it.second);
mod_data = mod_data + hierarchy_worker(mod_stat, it.first, level+1) * it.second;
mod_data.num_cells -= it.second;
} else {
mod_data.num_cells_by_type[it.first] += it.second;
}
return mod_data;
}
struct StatPass : public Pass {
@ -243,3 +243,4 @@ struct StatPass : public Pass {
}
} StatPass;
PRIVATE_NAMESPACE_END

4
passes/cmds/tee.cc
View file

@ -22,6 +22,9 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct TeePass : public Pass {
TeePass() : Pass("tee", "redirect command output to file") { }
virtual void help()
@ -86,3 +89,4 @@ struct TeePass : public Pass {
}
} TeePass;
PRIVATE_NAMESPACE_END

1
passes/cmds/trace.cc
View file

@ -20,6 +20,7 @@
#include "kernel/yosys.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct TraceMonitor : public RTLIL::Monitor

4
passes/cmds/write_file.cc
View file

@ -20,6 +20,9 @@
#include "kernel/yosys.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct WriteFileFrontend : public Frontend {
WriteFileFrontend() : Frontend("=write_file", "write a text to a file") { }
virtual void help()
@ -74,3 +77,4 @@ struct WriteFileFrontend : public Frontend {
}
} WriteFileFrontend;
PRIVATE_NAMESPACE_END