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https://github.com/YosysHQ/yosys
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Refactoring: Renamed RTLIL::Module::wires to wires_
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parent
d7916a49af
commit
f9946232ad
50 changed files with 191 additions and 191 deletions
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@ -46,8 +46,8 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
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if (chunk.wire != NULL) {
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std::string wire_name = chunk.wire->name;
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apply_prefix(prefix, wire_name);
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assert(module->wires.count(wire_name) > 0);
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chunk.wire = module->wires[wire_name];
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assert(module->wires_.count(wire_name) > 0);
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chunk.wire = module->wires_[wire_name];
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}
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sig = chunks;
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}
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@ -72,7 +72,7 @@ struct TechmapWorker
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if (module == NULL)
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return result;
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for (auto &it : module->wires) {
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for (auto &it : module->wires_) {
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const char *p = it.first.c_str();
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if (*p == '$')
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continue;
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@ -125,7 +125,7 @@ struct TechmapWorker
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std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
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for (auto &it : tpl->wires) {
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for (auto &it : tpl->wires_) {
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if (it.second->port_id > 0)
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positional_ports[stringf("$%d", it.second->port_id)] = it.first;
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std::string w_name = it.second->name;
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@ -145,12 +145,12 @@ struct TechmapWorker
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RTLIL::IdString portname = it.first;
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if (positional_ports.count(portname) > 0)
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portname = positional_ports.at(portname);
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if (tpl->wires.count(portname) == 0 || tpl->wires.at(portname)->port_id == 0) {
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if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
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if (portname.substr(0, 1) == "$")
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log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
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continue;
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}
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RTLIL::Wire *w = tpl->wires.at(portname);
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RTLIL::Wire *w = tpl->wires_.at(portname);
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RTLIL::SigSig c;
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if (w->port_output) {
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c.first = it.second;
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@ -265,7 +265,7 @@ struct TechmapWorker
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for (auto conn : cell->connections()) {
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if (conn.first.substr(0, 1) == "$")
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continue;
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if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0)
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if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
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continue;
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if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
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goto next_tpl;
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@ -388,7 +388,7 @@ struct TechmapWorker
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assert(!strncmp(q, "_TECHMAP_DO_", 12));
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std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
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while (tpl->wires.count(new_name))
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while (tpl->wires_.count(new_name))
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new_name += "_";
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tpl->rename(data.wire, new_name);
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