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Refactoring: Renamed RTLIL::Module::wires to wires_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
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2
passes/techmap/iopadmap.cc
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@ -118,7 +118,7 @@ struct IopadmapPass : public Pass {
if (!design->selected(module) || module->get_bool_attribute("\\blackbox"))
continue;
for (auto &it2 : module->wires)
for (auto &it2 : module->wires_)
{
RTLIL::Wire *wire = it2.second;