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Refactoring: Renamed RTLIL::Module::wires to wires_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
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6
passes/techmap/extract.cc
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@ -271,7 +271,7 @@ namespace
}
// mark external signals (used in module ports)
for (auto &wire_it : mod->wires)
for (auto &wire_it : mod->wires_)
{
RTLIL::Wire *wire = wire_it.second;
if (wire->port_id > 0)
@ -300,7 +300,7 @@ namespace
RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++), needle->name);
// create cell ports
for (auto &it : needle->wires) {
for (auto &it : needle->wires_) {
RTLIL::Wire *wire = it.second;
if (wire->port_id > 0) {
for (int i = 0; i < wire->width; i++)
@ -742,7 +742,7 @@ struct ExtractPass : public Pass {
std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second);
for (auto &chunk : chunks)
if (chunk.wire != NULL)
chunk.wire = newMod->wires.at(chunk.wire->name);
chunk.wire = newMod->wires_.at(chunk.wire->name);
newCell->set(conn.first, chunks);
}
}