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Refactoring: Renamed RTLIL::Module::wires to wires_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
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8
passes/sat/sat.cc
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@ -94,7 +94,7 @@ struct SatHelper
RTLIL::SigSpec big_lhs, big_rhs;
for (auto &it : module->wires)
for (auto &it : module->wires_)
{
if (it.second->attributes.count("\\init") == 0)
continue;
@ -1158,19 +1158,19 @@ struct SatPass : public Pass {
log_cmd_error("The options -set-init-undef, -set-init-def, and -set-init-zero are exclusive!\n");
if (set_def_inputs) {
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (it.second->port_input)
sets_def.push_back(it.second->name);
}
if (show_inputs) {
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (it.second->port_input)
shows.push_back(it.second->name);
}
if (show_outputs) {
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (it.second->port_output)
shows.push_back(it.second->name);
}