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Refactoring: Renamed RTLIL::Module::wires to wires_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
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22
passes/sat/eval.cc
View file

@ -87,16 +87,16 @@ struct BruteForceEquivChecker
mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1)
{
log("Checking for equivialence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
for (auto &w : mod1->wires)
for (auto &w : mod1->wires_)
{
RTLIL::Wire *wire1 = w.second;
if (wire1->port_id == 0)
continue;
if (mod2->wires.count(wire1->name) == 0)
if (mod2->wires_.count(wire1->name) == 0)
log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", wire1->name.c_str());
RTLIL::Wire *wire2 = mod2->wires.at(wire1->name);
RTLIL::Wire *wire2 = mod2->wires_.at(wire1->name);
if (wire1->width != wire2->width || wire1->port_input != wire2->port_input || wire1->port_output != wire2->port_output)
log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", wire1->name.c_str());
@ -153,11 +153,11 @@ struct VlogHammerReporter
ez.assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
std::vector<int> y_vec = satgen.importDefSigSpec(module->wires.at("\\y"));
std::vector<int> y_vec = satgen.importDefSigSpec(module->wires_.at("\\y"));
std::vector<bool> y_values;
if (model_undef) {
std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wires.at("\\y"));
std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wires_.at("\\y"));
y_vec.insert(y_vec.end(), y_undef_vec.begin(), y_undef_vec.end());
}
@ -252,7 +252,7 @@ struct VlogHammerReporter
std::vector<RTLIL::State> bits(patterns[idx].bits.begin(), patterns[idx].bits.begin() + total_input_width);
for (int i = 0; i < int(inputs.size()); i++) {
RTLIL::Wire *wire = module->wires.at(inputs[i]);
RTLIL::Wire *wire = module->wires_.at(inputs[i]);
for (int j = input_widths[i]-1; j >= 0; j--) {
ce.set(RTLIL::SigSpec(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec(wire, j));
@ -268,10 +268,10 @@ struct VlogHammerReporter
}
}
if (module->wires.count("\\y") == 0)
if (module->wires_.count("\\y") == 0)
log_error("No output wire (y) found in module %s!\n", RTLIL::id2cstr(module->name));
RTLIL::SigSpec sig(module->wires.at("\\y"));
RTLIL::SigSpec sig(module->wires_.at("\\y"));
RTLIL::SigSpec undef;
while (!ce.eval(sig, undef)) {
@ -318,9 +318,9 @@ struct VlogHammerReporter
int width = -1;
RTLIL::IdString esc_name = RTLIL::escape_id(name);
for (auto mod : modules) {
if (mod->wires.count(esc_name) == 0)
if (mod->wires_.count(esc_name) == 0)
log_error("Can't find input %s in module %s!\n", name.c_str(), RTLIL::id2cstr(mod->name));
RTLIL::Wire *port = mod->wires.at(esc_name);
RTLIL::Wire *port = mod->wires_.at(esc_name);
if (!port->port_input || port->port_output)
log_error("Wire %s in module %s is not an input!\n", name.c_str(), RTLIL::id2cstr(mod->name));
if (width >= 0 && width != port->width)
@ -469,7 +469,7 @@ struct EvalPass : public Pass {
}
if (shows.size() == 0) {
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (it.second->port_output)
shows.push_back(it.second->name);
}

22
passes/sat/expose.cc
View file

@ -87,7 +87,7 @@ static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *modu
dffsignals.add(sigmap(it.second->get("\\Q")));
}
for (auto &it : module->wires) {
for (auto &it : module->wires_) {
if (dffsignals.check_any(it.second))
dff_wires.insert(it.first);
}
@ -161,7 +161,7 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
}
std::map<std::string, dff_map_info_t> empty_dq_map;
for (auto &it : module->wires)
for (auto &it : module->wires_)
{
if (!consider_wire(it.second, empty_dq_map))
continue;
@ -321,7 +321,7 @@ struct ExposePass : public Pass {
for (auto &it : shared_dff_wires) {
if (!dff_dq_maps[mod_it.second].count(it))
continue;
if (!compare_wires(first_module->wires.at(it), mod_it.second->wires.at(it)))
if (!compare_wires(first_module->wires_.at(it), mod_it.second->wires_.at(it)))
continue;
new_shared_dff_wires.insert(it);
}
@ -365,7 +365,7 @@ struct ExposePass : public Pass {
if (first_module == NULL)
{
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (design->selected(module, it.second) && consider_wire(it.second, dff_dq_maps[module]))
if (!flag_dff || dff_wires.count(it.first))
shared_wires.insert(it.first);
@ -385,16 +385,16 @@ struct ExposePass : public Pass {
{
RTLIL::Wire *wire;
if (module->wires.count(it) == 0)
if (module->wires_.count(it) == 0)
goto delete_shared_wire;
wire = module->wires.at(it);
wire = module->wires_.at(it);
if (!design->selected(module, wire))
goto delete_shared_wire;
if (!consider_wire(wire, dff_dq_maps[module]))
goto delete_shared_wire;
if (!compare_wires(first_module->wires.at(it), wire))
if (!compare_wires(first_module->wires_.at(it), wire))
goto delete_shared_wire;
if (flag_dff && !dff_wires.count(it))
goto delete_shared_wire;
@ -449,7 +449,7 @@ struct ExposePass : public Pass {
SigMap out_to_in_map;
for (auto &it : module->wires)
for (auto &it : module->wires_)
{
if (flag_shared) {
if (shared_wires.count(it.first) == 0)
@ -491,10 +491,10 @@ struct ExposePass : public Pass {
for (auto &dq : dff_dq_maps[module])
{
if (!module->wires.count(dq.first))
if (!module->wires_.count(dq.first))
continue;
RTLIL::Wire *wire = module->wires.at(dq.first);
RTLIL::Wire *wire = module->wires_.at(dq.first);
std::set<RTLIL::SigBit> wire_bits_set = sigmap(wire).to_sigbit_set();
std::vector<RTLIL::SigBit> wire_bits_vec = sigmap(wire).to_sigbit_vector();
@ -587,7 +587,7 @@ struct ExposePass : public Pass {
{
RTLIL::Module *mod = design->modules.at(cell->type);
for (auto &it : mod->wires)
for (auto &it : mod->wires_)
{
RTLIL::Wire *p = it.second;
if (!p->port_input && !p->port_output)

2
passes/sat/freduce.cc
View file

@ -602,7 +602,7 @@ struct FreduceWorker
int bits_full_total = 0;
std::vector<std::set<RTLIL::SigBit>> batches;
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (it.second->port_input) {
batches.push_back(sigmap(it.second).to_sigbit_set());
bits_full_total += it.second->width;

14
passes/sat/miter.cc
View file

@ -73,13 +73,13 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
RTLIL::Module *gold_module = design->modules.at(gold_name);
RTLIL::Module *gate_module = design->modules.at(gate_name);
for (auto &it : gold_module->wires) {
for (auto &it : gold_module->wires_) {
RTLIL::Wire *w1 = it.second, *w2;
if (w1->port_id == 0)
continue;
if (gate_module->wires.count(it.second->name) == 0)
if (gate_module->wires_.count(it.second->name) == 0)
goto match_gold_port_error;
w2 = gate_module->wires.at(it.second->name);
w2 = gate_module->wires_.at(it.second->name);
if (w1->port_input != w2->port_input)
goto match_gold_port_error;
if (w1->port_output != w2->port_output)
@ -91,13 +91,13 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
log_cmd_error("No matching port in gate module was found for %s!\n", it.second->name.c_str());
}
for (auto &it : gate_module->wires) {
for (auto &it : gate_module->wires_) {
RTLIL::Wire *w1 = it.second, *w2;
if (w1->port_id == 0)
continue;
if (gold_module->wires.count(it.second->name) == 0)
if (gold_module->wires_.count(it.second->name) == 0)
goto match_gate_port_error;
w2 = gold_module->wires.at(it.second->name);
w2 = gold_module->wires_.at(it.second->name);
if (w1->port_input != w2->port_input)
goto match_gate_port_error;
if (w1->port_output != w2->port_output)
@ -120,7 +120,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
RTLIL::SigSpec all_conditions;
for (auto &it : gold_module->wires)
for (auto &it : gold_module->wires_)
{
RTLIL::Wire *w1 = it.second;

8
passes/sat/sat.cc
View file

@ -94,7 +94,7 @@ struct SatHelper
RTLIL::SigSpec big_lhs, big_rhs;
for (auto &it : module->wires)
for (auto &it : module->wires_)
{
if (it.second->attributes.count("\\init") == 0)
continue;
@ -1158,19 +1158,19 @@ struct SatPass : public Pass {
log_cmd_error("The options -set-init-undef, -set-init-def, and -set-init-zero are exclusive!\n");
if (set_def_inputs) {
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (it.second->port_input)
sets_def.push_back(it.second->name);
}
if (show_inputs) {
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (it.second->port_input)
shows.push_back(it.second->name);
}
if (show_outputs) {
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (it.second->port_output)
shows.push_back(it.second->name);
}