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Refactoring: Renamed RTLIL::Module::wires to wires_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
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2
passes/opt/opt_share.cc
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@ -237,7 +237,7 @@ struct OptShareWorker
assign_map.set(module);
dff_init_map.set(module);
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (it.second->attributes.count("\\init") != 0)
dff_init_map.add(it.second, it.second->attributes.at("\\init"));