mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Refactoring: Renamed RTLIL::Module::wires to wires_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/memory/memory_share.cc
View file

@ -137,7 +137,7 @@ struct MemoryShareWorker
std::map<RTLIL::SigBit, std::set<RTLIL::SigBit>> muxtree_upstream_map;
std::set<RTLIL::SigBit> non_feedback_nets;
for (auto wire_it : module->wires)
for (auto wire_it : module->wires_)
if (wire_it.second->port_output) {
std::vector<RTLIL::SigBit> bits = RTLIL::SigSpec(wire_it.second);
non_feedback_nets.insert(bits.begin(), bits.end());