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Refactoring: Renamed RTLIL::Module::wires to wires_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
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8
passes/hierarchy/hierarchy.cc
View file

@ -221,15 +221,15 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
std::string portname = conn.first;
if (portname.substr(0, 1) == "$") {
int port_id = atoi(portname.substr(1).c_str());
for (auto &wire_it : mod->wires)
for (auto &wire_it : mod->wires_)
if (wire_it.second->port_id == port_id) {
portname = wire_it.first;
break;
}
}
if (mod->wires.count(portname) == 0)
if (mod->wires_.count(portname) == 0)
log_error("Array cell `%s.%s' connects to unkown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
int port_size = mod->wires.at(portname)->width;
int port_size = mod->wires_.at(portname)->width;
if (conn_size == port_size)
continue;
if (conn_size != port_size*num)
@ -492,7 +492,7 @@ struct HierarchyPass : public Pass {
}
for (auto module : pos_mods)
for (auto &wire_it : module->wires) {
for (auto &wire_it : module->wires_) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_id > 0)
pos_map[std::pair<RTLIL::Module*,int>(module, wire->port_id)] = wire->name;

2
passes/hierarchy/submod.cc
View file

@ -212,7 +212,7 @@ struct SubmodWorker
if (opt_name.empty())
{
for (auto &it : module->wires)
for (auto &it : module->wires_)
it.second->attributes.erase("\\submod");
for (auto &it : module->cells)